mf plus info with detect sl mode (#695)

[proxmark3-svn] / fpga / fpga.ucf

diff --git a/fpga/fpga.ucf b/fpga/fpga.ucf
index 35f38e7364b9f5fa181a6b9f8b2ec2d11377f31b..f20e2da0255f1357b48c7663f3aa606143d3b44a 100644 (file)
--- a/fpga/fpga.ucf
+++ b/fpga/fpga.ucf
@@ -39,3 +39,16 @@ NET "ssp_frame"  LOC = "P31"  ;
 #PACE: Start of PACE Prohibit Constraints
 
 #PACE: End of Constraints generated by PACE
+
+# definition of Clock nets:
+NET "ck_1356meg" TNM_NET = "clk_net_1356" ;
+NET "ck_1356megb" TNM_NET = "clk_net_1356b" ;
+NET "pck0" TNM_NET = "clk_net_pck0" ;
+NET "spck" TNM_NET = "clk_net_spck" ;
+
+# Timing specs of clock nets:
+TIMEGRP "clk_net_1356_all" = "clk_net_1356" "clk_net_1356b" ;
+TIMESPEC "TS_1356MHz" = PERIOD "clk_net_1356_all" 74 ns HIGH 37 ns ;
+TIMESPEC "TS_24MHz" = PERIOD "clk_net_pck0" 42 ns HIGH 21 ns ;
+TIMESPEC "TS_4MHz" = PERIOD "clk_net_spck" 250 ns HIGH 125 ns ;
+