Re-enable -Wall

[proxmark3-svn] / armsrc / fpgaloader.c

diff --git a/armsrc/fpgaloader.c b/armsrc/fpgaloader.c
index 88fdc4cfc08a6517e092ef2aa892936fdb447285..86a7a405bda53009cb94d6cd2891e8a0f018df47 100644 (file)
--- a/armsrc/fpgaloader.c
+++ b/armsrc/fpgaloader.c
@@ -135,11 +135,24 @@ void FpgaSetupSscDma(BYTE *buf, int len)
        PDC_CONTROL(SSC_BASE) = PDC_RX_ENABLE;\r
 }\r
 \r
        PDC_CONTROL(SSC_BASE) = PDC_RX_ENABLE;\r
 }\r
 \r

-// Download the fpga image starting at FpgaImage and with length FpgaImageLen DWORDs (e.g. 4 bytes)\r
+static void DownloadFPGA_byte(unsigned char w)\r
+{\r
+#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }\r
+       SEND_BIT(7);\r
+       SEND_BIT(6);\r
+       SEND_BIT(5);\r
+       SEND_BIT(4);\r
+       SEND_BIT(3);\r
+       SEND_BIT(2);\r
+       SEND_BIT(1);\r
+       SEND_BIT(0);\r
+}\r
+\r
+// Download the fpga image starting at FpgaImage and with length FpgaImageLen bytes\r

 // If bytereversal is set: reverse the byte order in each 4-byte word\r
 // If bytereversal is set: reverse the byte order in each 4-byte word\r

-static void DownloadFPGA(const DWORD *FpgaImage, DWORD FpgaImageLen, int bytereversal)\r
+static void DownloadFPGA(const char *FpgaImage, int FpgaImageLen, int bytereversal)\r

 {\r
 {\r

-       int i, j;\r
+       int i;\r

 \r
        PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON);\r
        PIO_ENABLE = (1 << GPIO_FPGA_ON);\r
 \r
        PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON);\r
        PIO_ENABLE = (1 << GPIO_FPGA_ON);\r


@@ -161,24 +174,21 @@ static void DownloadFPGA(const DWORD *FpgaImage, DWORD FpgaImageLen, int byterev
        SpinDelay(50);\r
        HIGH(GPIO_FPGA_NPROGRAM);\r
 \r
        SpinDelay(50);\r
        HIGH(GPIO_FPGA_NPROGRAM);\r
 \r

-       for(i = 0; i < FpgaImageLen; i++) {\r
-               DWORD v = FpgaImage[i];\r
-               unsigned char w;\r
-               for(j = 0; j < 4; j++) {\r
-                       if(!bytereversal) \r
-                               w = v >>(j*8);\r
-                       else\r
-                               w = v >>((3-j)*8);\r
-#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }\r
-                       SEND_BIT(7);\r
-                       SEND_BIT(6);\r
-                       SEND_BIT(5);\r
-                       SEND_BIT(4);\r
-                       SEND_BIT(3);\r
-                       SEND_BIT(2);\r
-                       SEND_BIT(1);\r
-                       SEND_BIT(0);\r
+       if(bytereversal) {\r
+               /* This is only supported for DWORD aligned images */\r
+               if( ((int)FpgaImage % sizeof(DWORD)) == 0 ) {\r
+                       i=0;\r
+                       while(FpgaImageLen-->0)\r
+                               DownloadFPGA_byte(FpgaImage[(i++)^0x3]);\r
+                       /* Explanation of the magic in the above line: \r
+                        * i^0x3 inverts the lower two bits of the integer i, counting backwards\r
+                        * for each 4 byte increment. The generated sequence of (i++)^3 is\r
+                        * 3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12 etc. pp. 
+                        */\r

                }\r
                }\r

+       } else {\r
+               while(FpgaImageLen-->0)\r
+                       DownloadFPGA_byte(*FpgaImage++);\r

        }\r
 \r
        LED_D_OFF();\r
        }\r
 \r
        LED_D_OFF();\r


@@ -268,21 +278,21 @@ void FpgaDownloadAndGo(void)
                void *bitstream_start;\r
                unsigned int bitstream_length;\r
                if(bitparse_find_section('e', &bitstream_start, &bitstream_length)) {\r
                void *bitstream_start;\r
                unsigned int bitstream_length;\r
                if(bitparse_find_section('e', &bitstream_start, &bitstream_length)) {\r

-                       DownloadFPGA((DWORD *)bitstream_start, bitstream_length/4, 0);\r
+                       DownloadFPGA(bitstream_start, bitstream_length, 0);\r

                        \r
                        return; /* All done */\r
                }\r
        }\r
        \r
        /* Fallback for the old flash image format: Check for the magic marker 0xFFFFFFFF\r
                        \r
                        return; /* All done */\r
                }\r
        }\r
        \r
        /* Fallback for the old flash image format: Check for the magic marker 0xFFFFFFFF\r

-        * 0xAA995566 at address 0x2000. This is raw bitstream with a size of 336,768 bits \r
+        * 0xAA995566 at address 0x102000. This is raw bitstream with a size of 336,768 bits \r

         * = 10,524 DWORDs, stored as DWORDS e.g. little-endian in memory, but each DWORD\r
         * is still to be transmitted in MSBit first order. Set the invert flag to indicate\r
         * that the DownloadFPGA function should invert every 4 byte sequence when doing\r
         * the bytewise download.
         */\r
         * = 10,524 DWORDs, stored as DWORDS e.g. little-endian in memory, but each DWORD\r
         * is still to be transmitted in MSBit first order. Set the invert flag to indicate\r
         * that the DownloadFPGA function should invert every 4 byte sequence when doing\r
         * the bytewise download.
         */\r

-       if( *(DWORD*)0x2000 == 0xFFFFFFFF && *(DWORD*)0x2004 == 0xAA995566 )\r
-               DownloadFPGA((DWORD *)0x2000, 10524, 1);\r
+       if( *(DWORD*)0x102000 == 0xFFFFFFFF && *(DWORD*)0x102004 == 0xAA995566 )\r
+               DownloadFPGA((char*)0x102000, 10524*4, 1);\r

 }\r
 \r
 void FpgaGatherVersion(char *dst, int len)\r
 }\r
 \r
 void FpgaGatherVersion(char *dst, int len)\r