#include "../include/proxmark3.h"
#include "apps.h"
#include "util.h"
-#include "../include/hitag2.h"
#include "../common/crc16.h"
+#include "../common/lfdemod.h"
#include "string.h"
#include "crapto1.h"
-#include "mifareutil.h"
+#include "mifareutil.h"
+#include "../include/hitag2.h"
+
+// Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
+// TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
+// Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
+// T0 = TIMER_CLOCK1 / 125000 = 192
+#define T0 192
#define SHORT_COIL() LOW(GPIO_SSC_DOUT)
#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
// split into two routines so we can avoid timing issues after sending commands //
void DoAcquisition125k_internal(int trigger_threshold, bool silent)
{
- uint8_t *dest = mifare_get_bigbufptr();
- int n = 24000;
- int i = 0;
- memset(dest, 0x00, n);
+ uint8_t *dest = (uint8_t *)BigBuf;
+ uint16_t i = 0;
+ memset(dest, 0x00, BIGBUF_SIZE);
for(;;) {
if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
continue;
else
trigger_threshold = -1;
- if (++i >= n) break;
+ if (++i >= BIGBUF_SIZE) break;
}
}
if (!silent){
void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
{
-
- /* Make sure the tag is reset */
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+
+ /* Make sure the tag is reset */
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
SpinDelay(2500);
- int divisor_used = 95; // 125 KHz
+ int divisor = 95; // 125 KHz
// see if 'h' was specified
-
if (command[strlen((char *) command) - 1] == 'h')
- divisor_used = 88; // 134.8 KHz
+ divisor = 88; // 134.8 KHz
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
// Give it a bit of time for the resonant antenna to settle.
- SpinDelay(50);
-
-
- // And a little more time for the tag to fully power up
SpinDelay(2000);
// Now set up the SSC to get the ADC samples that are now streaming at us.
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
LED_D_OFF();
SpinDelayUs(delay_off);
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
LED_D_ON();
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
LED_D_OFF();
SpinDelayUs(delay_off);
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
-
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
// now do the read
signed char *dest = (signed char *)BigBuf;
int n = sizeof(BigBuf);
-// int *dest = GraphBuffer;
-// int n = GraphTraceLen;
// 128 bit shift register [shift3:shift2:shift1:shift0]
uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
DbpString("Now use tiread to check");
}
-void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
+
+
+// PIO_CODR = Clear Output Data Register
+// PIO_SODR = Set Output Data Register
+//#define LOW(x) AT91C_BASE_PIOA->PIO_CODR = (x)
+//#define HIGH(x) AT91C_BASE_PIOA->PIO_SODR = (x)
+void SimulateTagLowFrequency( uint16_t period, uint32_t gap, uint8_t ledcontrol)
{
- int i = 0;
- uint8_t *buff = (uint8_t *)BigBuf;
+ LED_D_ON();
+
+ uint16_t i = 0;
+ uint8_t send = 0;
+
+ //int overflow = 0;
+ uint8_t *buf = (uint8_t *)BigBuf;
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
- //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
+ SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+ RELAY_OFF();
- // Connect the A/D to the peak-detected low-frequency path.
- //SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
-
- // Configure output and enable pin that is connected to the FPGA (for modulating)
- AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
- AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; // (PIO_PER) PIO Enable Register ,
- AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; // (PIO_OER) Output Enable Register
- AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK; // (PIO_ODR) Output Disable Register
+ // Configure output pin that is connected to the FPGA (for modulating)
+ AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
+ AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
- // Give it a bit of time for the resonant antenna to settle.
- SpinDelay(150);
+ SHORT_COIL();
+
+ // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
+ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
+
+ // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames
+ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
+ AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
+
+ // Disable timer during configuration
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
- while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high
- while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK); // wait for ssp_clk to go low
+ // Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
+ // external trigger rising edge, load RA on rising edge of TIOA.
+ AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_RISING | AT91C_TC_ABETRG | AT91C_TC_LDRA_RISING;
+ // Enable and reset counter
+ //AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+
while(!BUTTON_PRESS()) {
WDT_HIT();
-
- // PIO_PDSR = Pin Data Status Register
- // GPIO_SSC_CLK = SSC Transmit Clock
- while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) { // wait for ssp_clk to go high
- if(BUTTON_PRESS()) {
- DbpString("Stopped at 0");
- FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
- return;
- }
- WDT_HIT();
- }
-
- // PIO_CODR = Clear Output Data Register
- // PIO_SODR = Set Output Data Register
- //#define LOW(x) AT91C_BASE_PIOA->PIO_CODR = (x)
- //#define HIGH(x) AT91C_BASE_PIOA->PIO_SODR = (x)
- if ( buff[i] > 0 ){
- HIGH(GPIO_SSC_DOUT);
- //FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
- //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
- } else {
+ // Receive frame, watch for at most T0*EOF periods
+ while (AT91C_BASE_TC1->TC_CV < T0 * 55) {
+
+ // Check if rising edge in modulation is detected
+ if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
+ // Retrieve the new timing values
+ //int ra = (AT91C_BASE_TC1->TC_RA/T0) + overflow;
+ //Dbprintf("Timing value - %d %d", ra, overflow);
+ //overflow = 0;
+
+ // Reset timer every frame, we have to capture the last edge for timing
+ AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+ send = 1;
+
+ LED_B_ON();
+ }
+ }
+
+ if ( send ) {
+ // Disable timer 1 with external trigger to avoid triggers during our own modulation
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
+
+ // Wait for HITAG_T_WAIT_1 carrier periods after the last reader bit,
+ // not that since the clock counts since the rising edge, but T_Wait1 is
+ // with respect to the falling edge, we need to wait actually (T_Wait1 - T_Low)
+ // periods. The gap time T_Low varies (4..10). All timer values are in
+ // terms of T0 units
+ while(AT91C_BASE_TC0->TC_CV < T0 * 16 );
+
+ // datat kommer in som 1 bit för varje position i arrayn
+ for(i = 0; i < period; ++i) {
+
+ // Reset clock for the next bit
+ AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
+
+ if ( buf[i] > 0 )
+ HIGH(GPIO_SSC_DOUT);
+ else
+ LOW(GPIO_SSC_DOUT);
+
+ while(AT91C_BASE_TC0->TC_CV < T0 * 1 );
+ }
+ // Drop modulation
LOW(GPIO_SSC_DOUT);
- //FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+
+ // Enable and reset external trigger in timer for capturing future frames
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+ LED_B_OFF();
}
-
- while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) { // wait for ssp_clk to go low
- if(BUTTON_PRESS()) {
- DbpString("Stopped at 1");
- FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
- return;
- }
- WDT_HIT();
- }
- //SpinDelayUs(512);
+ send = 0;
+
+ // Save the timer overflow, will be 0 when frame was received
+ //overflow += (AT91C_BASE_TC1->TC_CV/T0);
- ++i;
- if(i == period) {
- i = 0;
- if (gap) {
- // turn of modulation
- LOW(GPIO_SSC_DOUT);
- // wait
- SpinDelay(gap);
- }
+ // Reset the timer to restart while-loop that receives frames
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
+ }
+
+ LED_B_OFF();
+ LED_D_OFF();
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
+ AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+
+ DbpString("Sim Stopped");
+}
+
+
+void SimulateTagLowFrequencyA(int len, int gap)
+{
+ uint8_t *buf = (uint8_t *)BigBuf;
+
+ FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_TOGGLE_MODE); // new izsh toggle mode!
+
+ // Connect the A/D to the peak-detected low-frequency path.
+ SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+
+ // Now set up the SSC to get the ADC samples that are now streaming at us.
+ FpgaSetupSsc();
+ SpinDelay(5);
+
+ AT91C_BASE_SSC->SSC_THR = 0x00;
+
+ int i = 0;
+ while(!BUTTON_PRESS()) {
+ WDT_HIT();
+ if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
+
+ if ( buf[i] > 0 )
+ AT91C_BASE_SSC->SSC_THR = 0x43;
+ else
+ AT91C_BASE_SSC->SSC_THR = 0x00;
+
+ ++i;
+ LED_A_ON();
+ if (i >= len){
+ i = 0;
+ }
+ }
+
+ if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
+ volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
+ (void)r;
+ LED_A_OFF();
}
}
- DbpString("Stopped");
+ DbpString("lf simulate stopped");
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
- return;
}
#define DEBUG_FRAME_CONTENTS 1
}
// compose fc/8 fc/10 waveform
-static void fc(int c, int *n) {
+static void fc(int c, uint16_t *n) {
uint8_t *dest = (uint8_t *)BigBuf;
int idx;
// for when we want an fc8 pattern every 4 logical bits
- if(c==0) {
+ if(c == 0) {
dest[((*n)++)]=1;
dest[((*n)++)]=1;
dest[((*n)++)]=0;
dest[((*n)++)]=0;
}
// an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
- if(c==8) {
+ if(c == 8) {
for (idx=0; idx<6; idx++) {
dest[((*n)++)]=1;
dest[((*n)++)]=1;
}
// an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
- if(c==10) {
- for (idx=0; idx<5; idx++) {
+ if(c == 10) {
+ for (idx = 0; idx < 5; idx++) {
dest[((*n)++)]=1;
dest[((*n)++)]=1;
dest[((*n)++)]=1;
// prepare a waveform pattern in the buffer based on the ID given then
// simulate a HID tag until the button is pressed
-void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
+void CmdHIDsimTAG(int hi, int lo, uint8_t ledcontrol)
{
- int n=0, i=0;
+ uint16_t n = 0, i = 0;
/*
HID tag bitstream format
The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
*/
- if (hi>0xFFF) {
+ if (hi > 0xFFF) {
DbpString("Tags can only have 44 bits.");
return;
}
- fc(0,&n);
+ fc(0, &n);
// special start of frame marker containing invalid bit sequences
fc(8, &n); fc(8, &n); // invalid
fc(8, &n); fc(10, &n); // logical 0
WDT_HIT();
// manchester encode bits 43 to 32
- for (i=11; i>=0; i--) {
- if ((i%4)==3) fc(0,&n);
- if ((hi>>i)&1) {
+ for (i = 11; i >= 0; i--) {
+ if ((i % 4) == 3) fc(0, &n);
+ if ((hi >> i) & 1) {
fc(10, &n); fc(8, &n); // low-high transition
} else {
fc(8, &n); fc(10, &n); // high-low transition
WDT_HIT();
// manchester encode bits 31 to 0
- for (i=31; i>=0; i--) {
- if ((i%4)==3) fc(0,&n);
- if ((lo>>i)&1) {
+ for (i = 31; i >= 0; i--) {
+ if ((i % 4 ) == 3) fc(0, &n);
+ if ((lo >> i ) & 1) {
fc(10, &n); fc(8, &n); // low-high transition
} else {
fc(8, &n); fc(10, &n); // high-low transition
LED_A_OFF();
}
-size_t fsk_demod(uint8_t * dest, size_t size)
-{
- uint32_t last_transition = 0;
- uint32_t idx = 1;
-
- // we don't care about actual value, only if it's more or less than a
- // threshold essentially we capture zero crossings for later analysis
- uint8_t threshold_value = 127;
-
- // sync to first lo-hi transition, and threshold
-
- //Need to threshold first sample
- dest[0] = (dest[0] < threshold_value) ? 0 : 1;
-
- size_t numBits = 0;
- // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
- // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
- // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
- for(idx = 1; idx < size; idx++) {
- // threshold current value
- dest[idx] = (dest[idx] < threshold_value) ? 0 : 1;
-
- // Check for 0->1 transition
- if (dest[idx-1] < dest[idx]) { // 0 -> 1 transition
-
- dest[numBits] = (idx-last_transition < 9) ? 1 : 0;
- last_transition = idx;
- numBits++;
- }
- }
- return numBits; //Actually, it returns the number of bytes, but each byte represents a bit: 1 or 0
-}
-
-
-size_t aggregate_bits(uint8_t *dest,size_t size, uint8_t h2l_crossing_value,uint8_t l2h_crossing_value, uint8_t maxConsequtiveBits )
-{
- uint8_t lastval=dest[0];
- uint32_t idx=0;
- size_t numBits=0;
- uint32_t n=1;
-
- for( idx=1; idx < size; idx++) {
-
- if (dest[idx]==lastval) {
- n++;
- continue;
- }
- //if lastval was 1, we have a 1->0 crossing
- if ( dest[idx-1] ) {
- n=(n+1) / h2l_crossing_value;
- } else {// 0->1 crossing
- n=(n+1) / l2h_crossing_value;
- }
- if (n == 0) n = 1;
-
- if(n < maxConsequtiveBits)
- {
- memset(dest+numBits, dest[idx-1] , n);
- numBits += n;
- }
- n=0;
- lastval=dest[idx];
- }//end for
-
- return numBits;
-
-}
-// loop to capture raw HID waveform then FSK demodulate the TAG ID from it
+// loop to get raw HID waveform then FSK demodulate the TAG ID from it
void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
{
uint8_t *dest = (uint8_t *)BigBuf;
-
- size_t size=0,idx=0; //, found=0;
- uint32_t hi2=0, hi=0, lo=0;
+ uint32_t hi2 = 0, hi = 0, lo = 0;
// Configure to go in 125Khz listen mode
LFSetupFPGAForADC(0, true);
if (ledcontrol) LED_A_ON();
DoAcquisition125k_internal(-1,true);
- size = sizeof(BigBuf);
// FSK demodulator
- size = fsk_demod(dest, size);
-
- // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
- // 1->0 : fc/8 in sets of 6
- // 0->1 : fc/10 in sets of 5
- size = aggregate_bits(dest,size, 6,5,5);
+ int bitLen = HIDdemodFSK(dest,BIGBUF_SIZE,&hi2,&hi,&lo);
WDT_HIT();
+ if (bitLen > 0 && lo > 0){
+
// final loop, go over previously decoded manchester data and decode into usable tag ID
// 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
- uint8_t frame_marker_mask[] = {1,1,1,0,0,0};
- int numshifts = 0;
- idx = 0;
- while( idx + sizeof(frame_marker_mask) < size) {
- // search for a start of frame marker
- if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
- { // frame marker found
- idx+=sizeof(frame_marker_mask);
-
- while(dest[idx] != dest[idx+1] && idx < size-2)
- {
- // Keep going until next frame marker (or error)
- // Shift in a bit. Start by shifting high registers
- hi2=(hi2<<1)|(hi>>31);
- hi=(hi<<1)|(lo>>31);
- //Then, shift in a 0 or one into low
- if (dest[idx] && !dest[idx+1]) // 1 0
- lo=(lo<<1)|0;
- else // 0 1
- lo=(lo<<1)|
- 1;
- numshifts ++;
- idx += 2;
- }
- //Dbprintf("Num shifts: %d ", numshifts);
- // Hopefully, we read a tag and hit upon the next frame marker
- if(idx + sizeof(frame_marker_mask) < size)
- {
- if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
- {
- if (hi2 != 0){
- Dbprintf("TAG ID: %x%08x%08x (%d)",
- (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+
+ if (hi2 != 0){
+ //extra large HID tags
+ Dbprintf("TAG ID: %x%08x%08x (%d)",
+ (unsigned int) hi2,
+ (unsigned int) hi,
+ (unsigned int) lo,
+ (unsigned int) (lo >> 1) & 0xFFFF);
+
+ } else {
+ //standard HID tags <38 bits
+ uint8_t bitlen = 0;
+ uint32_t fc = 0;
+ uint32_t cardnum = 0;
+
+ if ((( hi >> 5 ) & 1) ==1){//if bit 38 is set then < 37 bit format is used
+ uint32_t lo2 = 0;
+ lo2 = (((hi & 31) << 12) | (lo >> 20)); //get bits 21-37 to check for format len bit
+ uint8_t idx3 = 1;
+ while(lo2 > 1){ //find last bit set to 1 (format len bit)
+ lo2 = lo2 >> 1;
+ idx3++;
}
- else {
- Dbprintf("TAG ID: %x%08x (%d)",
- (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+ bitlen =idx3 + 19;
+ fc = 0;
+ cardnum = 0;
+ if(bitlen == 26){
+ cardnum = (lo >> 1) & 0xFFFF;
+ fc = (lo >> 17) & 0xFF;
+ }
+ if(bitlen == 37){
+ cardnum = (lo >> 1) & 0x7FFFF;
+ fc = ((hi & 0xF) << 12)|( lo >> 20);
+ }
+ if(bitlen == 34){
+ cardnum = (lo >> 1) & 0xFFFF;
+ fc = ((hi & 1) << 15) | (lo >> 17);
+ }
+ if(bitlen == 35){
+ cardnum = (lo >> 1 ) & 0xFFFFF;
+ fc = ((hi & 1) << 11 ) | ( lo >> 21);
}
}
-
+ else { //if bit 38 is not set then 37 bit format is used
+ bitlen = 37;
+ fc = 0;
+ cardnum = 0;
+ if(bitlen == 37){
+ cardnum = ( lo >> 1) & 0x7FFFF;
+ fc = ((hi & 0xF) << 12 ) |(lo >> 20);
+ }
}
-
- // reset
- hi2 = hi = lo = 0;
- numshifts = 0;
- }else
- {
- idx++;
+ Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
+ (unsigned int) hi,
+ (unsigned int) lo,
+ (unsigned int) (lo >> 1) & 0xFFFF,
+ (unsigned int) bitlen,
+ (unsigned int) fc,
+ (unsigned int) cardnum);
}
+ if (findone){
+ if (ledcontrol) LED_A_OFF();
+ return;
+ }
+ // reset
+ hi2 = hi = lo = 0;
}
WDT_HIT();
-
- }
+ }
DbpString("Stopped");
if (ledcontrol) LED_A_OFF();
}
-uint32_t bytebits_to_byte(uint8_t* src, int numbits)
+void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
{
- uint32_t num = 0;
- for(int i = 0 ; i < numbits ; i++)
- {
- num = (num << 1) | (*src);
- src++;
+ uint8_t *dest = (uint8_t *)BigBuf;
+ uint32_t bitLen = 0;
+ int clk = 0, invert = 0, errCnt = 0;
+ uint64_t lo = 0;
+
+ // Configure to go in 125Khz listen mode
+ LFSetupFPGAForADC(0, true);
+
+ while(!BUTTON_PRESS()) {
+
+ WDT_HIT();
+ if (ledcontrol) LED_A_ON();
+
+ DoAcquisition125k_internal(-1,true);
+
+ // FSK demodulator
+ bitLen = BIGBUF_SIZE;
+ errCnt = askmandemod(dest,&bitLen,&clk,&invert);
+ if ( errCnt < 0 ) continue;
+
+ WDT_HIT();
+
+ lo = Em410xDecode(dest,bitLen);
+
+ if ( lo <= 0) continue;
+
+ Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
+ (uint32_t)(lo >> 32),
+ (uint32_t)lo,
+ (uint32_t)(lo & 0xFFFF),
+ (uint32_t)((lo >> 16LL) & 0xFF),
+ (uint32_t)(lo & 0xFFFFFF)
+ );
+
+ if (findone){
+ if (ledcontrol) LED_A_OFF();
+ return;
+ }
+
+ WDT_HIT();
+ lo = clk = invert = errCnt = 0;
}
- return num;
+ DbpString("Stopped");
+ if (ledcontrol) LED_A_OFF();
}
-
void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
{
uint8_t *dest = (uint8_t *)BigBuf;
+ int idx = 0;
+ uint32_t code = 0, code2 = 0;
+ uint8_t version = 0;
+ uint8_t facilitycode = 0;
+ uint16_t number = 0;
- size_t size=0, idx=0;
- uint32_t code=0, code2=0;
-
- // Configure to go in 125Khz listen mode
LFSetupFPGAForADC(0, true);
while(!BUTTON_PRESS()) {
+
WDT_HIT();
if (ledcontrol) LED_A_ON();
- DoAcquisition125k_internal(-1,true);
- size = sizeof(BigBuf);
-
- // FSK demodulator
- size = fsk_demod(dest, size);
+ DoAcquisition125k_internal(-1, true);
- // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
- // 1->0 : fc/8 in sets of 7
- // 0->1 : fc/10 in sets of 6
- size = aggregate_bits(dest, size, 7,6,13);
-
- WDT_HIT();
-
- //Handle the data
- uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1};
- for( idx=0; idx < size - 64; idx++) {
-
- if ( memcmp(dest + idx, mask, sizeof(mask)) ) continue;
-
- Dbprintf("%d%d%d%d%d%d%d%d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7]);
- Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+8], dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15]);
- Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+16],dest[idx+17],dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23]);
- Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+24],dest[idx+25],dest[idx+26],dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31]);
- Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35],dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39]);
- Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44],dest[idx+45],dest[idx+46],dest[idx+47]);
- Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53],dest[idx+54],dest[idx+55]);
- Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
+ idx = IOdemodFSK(dest, BIGBUF_SIZE);
- code = bytebits_to_byte(dest+idx,32);
- code2 = bytebits_to_byte(dest+idx+32,32);
+ if ( idx < 0 )
+ continue;
- short version = bytebits_to_byte(dest+idx+14,4);
- char unknown = bytebits_to_byte(dest+idx+19,8) ;
- uint16_t number = bytebits_to_byte(dest+idx+36,9);
-
- Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,unknown,number,code,code2);
- if (ledcontrol) LED_D_OFF();
-
- // if we're only looking for one tag
+ WDT_HIT();
+
+ //Index map
+ //0 10 20 30 40 50 60
+ //| | | | | | |
+ //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
+ //-----------------------------------------------------------------------------
+ //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
+ //
+ //XSF(version)facility:codeone+codetwo
+ //Handle the data
+
+ if(findone){ //only print binary if we are doing one
+ Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
+ Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
+ Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
+ Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
+ Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
+ Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
+ Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
+ }
+
+ code = bytebits_to_byte(dest+idx,32);
+ code2 = bytebits_to_byte(dest+idx+32,32);
+ version = bytebits_to_byte(dest+idx+27,8); //14,4
+ facilitycode = bytebits_to_byte(dest+idx+18,8) ;
+ number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
+
+ Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)", version, facilitycode, number, code, code2);
if (findone){
- LED_A_OFF();
- return;
+ if (ledcontrol) LED_A_OFF();
+ return;
}
+ code = code2 = 0;
+ version = facilitycode = 0;
+ number = 0;
+ idx = 0;
}
- WDT_HIT();
- }
+
DbpString("Stopped");
if (ledcontrol) LED_A_OFF();
}
// Read one card block in page 0
void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
{
- uint8_t *dest = mifare_get_bigbufptr();
+ uint8_t *dest = get_bigbufptr_recvrespbuf();
uint16_t bufferlength = T55xx_SAMPLES_SIZE;
uint32_t i = 0;
for(;;) {
if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
AT91C_BASE_SSC->SSC_THR = 0x43;
+ //AT91C_BASE_SSC->SSC_THR = 0xff;
LED_D_ON();
}
if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
++i;
LED_D_OFF();
- if (i > bufferlength) break;
+ if (i >= bufferlength) break;
}
}
// Read card traceability data (page 1)
void T55xxReadTrace(void){
- uint8_t *dest = mifare_get_bigbufptr();
+ uint8_t *dest = get_bigbufptr_recvrespbuf();
uint16_t bufferlength = T55xx_SAMPLES_SIZE;
- int i=0;
+ uint32_t i = 0;
// Clear destination buffer before sending the command 0x80 = average
memset(dest, 0x80, bufferlength);
block_done = 0;
half_switch = 0;
}
+ if(i < GraphTraceLen)
+ {
if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
else dir = 1;
}
+ }
if(bitidx==255)
bitidx=0;
warnings = 0;
void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
- uint8_t *dest = mifare_get_bigbufptr();
+ uint8_t *dest = get_bigbufptr_recvrespbuf();
uint16_t bufferlength = 12000;
uint32_t i = 0;
projects / proxmark3-svn / blobdiff