FIXED: Merged all Holimans code-review issues which should fix a lot of memoryleaks.

[proxmark3-svn] / armsrc / lfops.c

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index 76c4b44e7f1090c5193ceefdb2ae5ea269db407c..c80caf776b323d600453b62c557c5f4e4d90778f 100644 (file)
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -8,15 +8,21 @@
 // Also routines for raw mode reading/simulating of LF waveform
 //-----------------------------------------------------------------------------
 
 // Also routines for raw mode reading/simulating of LF waveform
 //-----------------------------------------------------------------------------
 

-#include "proxmark3.h"
+#include "../include/proxmark3.h"

 #include "apps.h"
 #include "util.h"
 #include "apps.h"
 #include "util.h"

-#include "hitag2.h"
-#include "crc16.h"
+#include "../include/hitag2.h"
+#include "../common/crc16.h"

 #include "string.h"
 #include "string.h"

+#include "crapto1.h"
+#include "mifareutil.h"

 
 

-void AcquireRawAdcSamples125k(int divisor)
+#define SHORT_COIL()   LOW(GPIO_SSC_DOUT)
+#define OPEN_COIL()            HIGH(GPIO_SSC_DOUT)
+
+void LFSetupFPGAForADC(int divisor, bool lf_field)

 {
 {

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

        if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
        else if (divisor == 0)
        if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
        else if (divisor == 0)


@@ -24,30 +30,38 @@ void AcquireRawAdcSamples125k(int divisor)
        else
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
 
        else
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
 

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));

 
        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
 
        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);

-
+       

        // Give it a bit of time for the resonant antenna to settle.
        // Give it a bit of time for the resonant antenna to settle.

-       SpinDelay(50);
-
+       SpinDelay(150);
+       

        // Now set up the SSC to get the ADC samples that are now streaming at us.
        FpgaSetupSsc();
        // Now set up the SSC to get the ADC samples that are now streaming at us.
        FpgaSetupSsc();

+}

 
 

-       // Now call the acquisition routine
+void AcquireRawAdcSamples125k(int divisor)
+{
+       LFSetupFPGAForADC(divisor, true);

        DoAcquisition125k();
 }
 
        DoAcquisition125k();
 }
 

+void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
+{
+       LFSetupFPGAForADC(divisor, false);
+       DoAcquisition125k_threshold(trigger_threshold);
+}
+

 // split into two routines so we can avoid timing issues after sending commands //
 // split into two routines so we can avoid timing issues after sending commands //

-void DoAcquisition125k(void)
+void DoAcquisition125k_internal(int trigger_threshold, bool silent)

 {
 {

-       uint8_t *dest = (uint8_t *)BigBuf;
-       int n = sizeof(BigBuf);
-       int i;
+       uint8_t *dest =  mifare_get_bigbufptr();
+       int n = 24000;
+       int i = 0;
+       memset(dest, 0x00, n);

 
 

-       memset(dest, 0, n);
-       i = 0;

        for(;;) {
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
                        AT91C_BASE_SSC->SSC_THR = 0x43;
        for(;;) {
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
                        AT91C_BASE_SSC->SSC_THR = 0x43;


@@ -55,38 +69,46 @@ void DoAcquisition125k(void)
                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

-                       i++;

                        LED_D_OFF();
                        LED_D_OFF();

-                       if (i >= n) break;
+                       if (trigger_threshold != -1 && dest[i] < trigger_threshold)
+                               continue;
+                       else
+                               trigger_threshold = -1;
+                       if (++i >= n) break;

                }
        }
                }
        }

-       Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
+       if (!silent){
+               Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",

                        dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
                        dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);

+       }

 }
 }

-
+void DoAcquisition125k_threshold(int trigger_threshold) {
+        DoAcquisition125k_internal(trigger_threshold, true);
+}
+void DoAcquisition125k() {
+        DoAcquisition125k_internal(-1, true);
+}      
+       

 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
 {
 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
 {

-       int at134khz;

 
        /* Make sure the tag is reset */
 
        /* Make sure the tag is reset */

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        SpinDelay(2500);
 
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        SpinDelay(2500);
 

+       int divisor_used = 95; // 125 KHz

        // see if 'h' was specified
        // see if 'h' was specified

-       if (command[strlen((char *) command) - 1] == 'h')
-               at134khz = TRUE;
-       else
-               at134khz = FALSE;
-
-       if (at134khz)
-               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-       else
-               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

 
 

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       if (command[strlen((char *) command) - 1] == 'h')
+               divisor_used = 88; // 134.8 KHz

 
 

+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); 
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

        // Give it a bit of time for the resonant antenna to settle.
        SpinDelay(50);
        // Give it a bit of time for the resonant antenna to settle.
        SpinDelay(50);

+       
+       

        // And a little more time for the tag to fully power up
        SpinDelay(2000);
 
        // And a little more time for the tag to fully power up
        SpinDelay(2000);
 


@@ -98,12 +120,9 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
                FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
                LED_D_OFF();
                SpinDelayUs(delay_off);
                FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
                LED_D_OFF();
                SpinDelayUs(delay_off);

-               if (at134khz)
-                       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-               else
-                       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); 

 
 

-               FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+               FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

                LED_D_ON();
                if(*(command++) == '0')
                        SpinDelayUs(period_0);
                LED_D_ON();
                if(*(command++) == '0')
                        SpinDelayUs(period_0);


@@ -113,15 +132,12 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        LED_D_OFF();
        SpinDelayUs(delay_off);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        LED_D_OFF();
        SpinDelayUs(delay_off);

-       if (at134khz)
-               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-       else
-               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); 

 
 

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

 
        // now do the read
 
        // now do the read

-       DoAcquisition125k();
+       DoAcquisition125k(-1);

 }
 
 /* blank r/w tag data stream
 }
 
 /* blank r/w tag data stream


@@ -158,6 +174,7 @@ void ReadTItag(void)
        uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
 
        // TI tags charge at 134.2Khz
        uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
 
        // TI tags charge at 134.2Khz

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
 
        // Place FPGA in passthrough mode, in this mode the CROSS_LO line
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
 
        // Place FPGA in passthrough mode, in this mode the CROSS_LO line


@@ -274,17 +291,17 @@ void WriteTIbyte(uint8_t b)
        {
                if (b&(1<<i)) {
                        // stop modulating antenna
        {
                if (b&(1<<i)) {
                        // stop modulating antenna

-                       LOW(GPIO_SSC_DOUT);
+                       SHORT_COIL();

                        SpinDelayUs(1000);
                        // modulate antenna
                        SpinDelayUs(1000);
                        // modulate antenna

-                       HIGH(GPIO_SSC_DOUT);
+                       OPEN_COIL();

                        SpinDelayUs(1000);
                } else {
                        // stop modulating antenna
                        SpinDelayUs(1000);
                } else {
                        // stop modulating antenna

-                       LOW(GPIO_SSC_DOUT);
+                       SHORT_COIL();

                        SpinDelayUs(300);
                        // modulate antenna
                        SpinDelayUs(300);
                        // modulate antenna

-                       HIGH(GPIO_SSC_DOUT);
+                       OPEN_COIL();

                        SpinDelayUs(1700);
                }
        }
                        SpinDelayUs(1700);
                }
        }


@@ -365,6 +382,7 @@ void AcquireTiType(void)
 // if not provided a valid crc will be computed from the data and written.
 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
 {
 // if not provided a valid crc will be computed from the data and written.
 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
 {

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);   

        if(crc == 0) {
                crc = update_crc16(crc, (idlo)&0xff);
                crc = update_crc16(crc, (idlo>>8)&0xff);
        if(crc == 0) {
                crc = update_crc16(crc, (idlo)&0xff);
                crc = update_crc16(crc, (idlo>>8)&0xff);


@@ -433,55 +451,57 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
 
 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 {
 
 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 {

-       int i;
-       uint8_t *tab = (uint8_t *)BigBuf;
-    
+       int i = 0;
+       uint8_t *buff = (uint8_t *)BigBuf;
+
+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);

-    
-       AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
-    
+       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+
+       // Configure output and enable pin that is connected to the FPGA (for modulating)
+       AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;    

        AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
        AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;

+       

        AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
        AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;

-    
-#define SHORT_COIL()   LOW(GPIO_SSC_DOUT)
-#define OPEN_COIL()            HIGH(GPIO_SSC_DOUT)
-    
-       i = 0;
-       for(;;) {
+
+       // Give it a bit of time for the resonant antenna to settle.
+       SpinDelay(30);
+
+       for(;;) { 
+               

                while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
                while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {

-                       if(BUTTON_PRESS()) {
-                               DbpString("Stopped");
-                               return;
-                       }
-                       WDT_HIT();
+                        if(BUTTON_PRESS()) {
+                                DbpString("Stopped at 0");
+                                FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+                                return;
+                        }
+                        WDT_HIT();

                }
         
                }
         

-               if (ledcontrol)
-                       LED_D_ON();
-        
-               if(tab[i])
+               if ( buff[i] )

                        OPEN_COIL();
                else
                        SHORT_COIL();
                        OPEN_COIL();
                else
                        SHORT_COIL();

-        
-               if (ledcontrol)
-                       LED_D_OFF();
-        
-               while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
-                       if(BUTTON_PRESS()) {
-                               DbpString("Stopped");
+       
+                while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
+                        if(BUTTON_PRESS()) {
+                               DbpString("Stopped at 1");
+                               FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

                                return;
                        }
                        WDT_HIT();
                                return;
                        }
                        WDT_HIT();

-               }
+                }

         
         

-               i++;
+               ++i;

                if(i == period) {
                        i = 0;
                        if (gap) {
                if(i == period) {
                        i = 0;
                        if (gap) {

+                               // turn of modulation

                                SHORT_COIL();
                                SHORT_COIL();

-                               SpinDelayUs(gap);
-                       }
+                               // wait
+                               SpinDelay(gap);
+                       } 

                }
        }
 }
                }
        }
 }


@@ -588,420 +608,213 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 
        if (ledcontrol)
                LED_A_ON();
 
        if (ledcontrol)
                LED_A_ON();

+       

        SimulateTagLowFrequency(n, 0, ledcontrol);
 
        if (ledcontrol)
                LED_A_OFF();
 }
 
        SimulateTagLowFrequency(n, 0, ledcontrol);
 
        if (ledcontrol)
                LED_A_OFF();
 }
 

-
-// loop to capture raw HID waveform then FSK demodulate the TAG ID from it
-void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
+size_t fsk_demod(uint8_t * dest, size_t size)

 {
 {

-       uint8_t *dest = (uint8_t *)BigBuf;
-       int m=0, n=0, i=0, idx=0, found=0, lastval=0;
-  uint32_t hi2=0, hi=0, lo=0;
+       uint32_t last_transition = 0;
+       uint32_t idx = 1;

 
 

-       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       // we don't care about actual value, only if it's more or less than a
+       // threshold essentially we capture zero crossings for later analysis
+       uint8_t threshold_value = 127;

 
 

-       // Connect the A/D to the peak-detected low-frequency path.
-       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+       // sync to first lo-hi transition, and threshold

 
 

-       // Give it a bit of time for the resonant antenna to settle.
-       SpinDelay(50);
+       //Need to threshold first sample
+       dest[0] = (dest[0] < threshold_value) ? 0 : 1;

 
 

-       // Now set up the SSC to get the ADC samples that are now streaming at us.
-       FpgaSetupSsc();
+       size_t numBits = 0;
+       // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
+       // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
+       // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
+       for(idx = 1; idx < size; idx++) {
+               // threshold current value
+               dest[idx] = (dest[idx] < threshold_value) ? 0 : 1;

 
 

-       for(;;) {
-               WDT_HIT();
-               if (ledcontrol)
-                       LED_A_ON();
-               if(BUTTON_PRESS()) {
-                       DbpString("Stopped");
-                       if (ledcontrol)
-                               LED_A_OFF();
-                       return;
-               }
+               // Check for 0->1 transition
+               if (dest[idx-1] < dest[idx]) { // 0 -> 1 transition

 
 

-               i = 0;
-               m = sizeof(BigBuf);
-               memset(dest,128,m);
-               for(;;) {
-                       if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
-                               AT91C_BASE_SSC->SSC_THR = 0x43;
-                               if (ledcontrol)
-                                       LED_D_ON();
-                       }
-                       if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
-                               dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
-                               // we don't care about actual value, only if it's more or less than a
-                               // threshold essentially we capture zero crossings for later analysis
-                               if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
-                               i++;
-                               if (ledcontrol)
-                                       LED_D_OFF();
-                               if(i >= m) {
-                                       break;
-                               }
-                       }
+                       dest[numBits] =  (idx-last_transition <  9) ? 1 : 0;
+                       last_transition = idx;
+                       numBits++;

                }
                }

+       }
+       return numBits; //Actually, it returns the number of bytes, but each byte represents a bit: 1 or 0
+}

 
 

-               // FSK demodulator

 
 

-               // sync to first lo-hi transition
-               for( idx=1; idx<m; idx++) {
-                       if (dest[idx-1]<dest[idx])
-                               lastval=idx;
-                               break;
-               }
-               WDT_HIT();
+size_t aggregate_bits(uint8_t *dest,size_t size, uint8_t h2l_crossing_value,uint8_t l2h_crossing_value, uint8_t maxConsequtiveBits )
+{
+       uint8_t lastval=dest[0];
+       uint32_t idx=0;
+       size_t numBits=0;
+       uint32_t n=1;

 
 

-               // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
-               // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
-               // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
-               for( i=0; idx<m; idx++) {
-                       if (dest[idx-1]<dest[idx]) {
-                               dest[i]=idx-lastval;
-                               if (dest[i] <= 8) {
-                                               dest[i]=1;
-                               } else {
-                                               dest[i]=0;
-                               }
+       for( idx=1; idx < size; idx++) {

 
 

-                               lastval=idx;
-                               i++;
-                       }
+               if (dest[idx]==lastval) {
+                       n++;
+                       continue;
+               }
+               //if lastval was 1, we have a 1->0 crossing
+               if ( dest[idx-1] ) {
+                       n=(n+1) / h2l_crossing_value;
+               } else {// 0->1 crossing
+                       n=(n+1) / l2h_crossing_value;
+               }
+               if (n == 0) n = 1;
+
+               if(n < maxConsequtiveBits)
+               {
+                       memset(dest+numBits, dest[idx-1] , n);
+                       numBits += n;

                }
                }

-               m=i;
+               n=0;
+               lastval=dest[idx];
+       }//end for
+
+       return numBits;
+
+}
+// loop to capture raw HID waveform then FSK demodulate the TAG ID from it
+void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
+{
+       uint8_t *dest = (uint8_t *)BigBuf;
+
+       size_t size=0,idx=0; //, found=0;
+  uint32_t hi2=0, hi=0, lo=0;
+
+       // Configure to go in 125Khz listen mode
+       LFSetupFPGAForADC(0, true);
+
+       while(!BUTTON_PRESS()) {
+

                WDT_HIT();
                WDT_HIT();

+               if (ledcontrol) LED_A_ON();
+
+               DoAcquisition125k_internal(-1,true);
+               size  = sizeof(BigBuf);
+
+               // FSK demodulator
+               size = fsk_demod(dest, size);

 
                // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
 
                // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns

-               lastval=dest[0];
-               idx=0;
-               i=0;
-               n=0;
-               for( idx=0; idx<m; idx++) {
-                       if (dest[idx]==lastval) {
-                               n++;
-                       } else {
-                               // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,
-                               // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets
-                               // swallowed up by rounding
-                               // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding
-                               // special start of frame markers use invalid manchester states (no transitions) by using sequences
-                               // like 111000
-                               if (dest[idx-1]) {
-                                       n=(n+1)/6;                      // fc/8 in sets of 6
-                               } else {
-                                       n=(n+1)/5;                      // fc/10 in sets of 5
-                               }
-                               switch (n) {                    // stuff appropriate bits in buffer
-                                       case 0:
-                                       case 1: // one bit
-                                               dest[i++]=dest[idx-1];
-                                               break;
-                                       case 2: // two bits
-                                               dest[i++]=dest[idx-1];
-                                               dest[i++]=dest[idx-1];
-                                               break;
-                                       case 3: // 3 bit start of frame markers
-                                               dest[i++]=dest[idx-1];
-                                               dest[i++]=dest[idx-1];
-                                               dest[i++]=dest[idx-1];
-                                               break;
-                                       // When a logic 0 is immediately followed by the start of the next transmisson
-                                       // (special pattern) a pattern of 4 bit duration lengths is created.
-                                       case 4:
-                                               dest[i++]=dest[idx-1];
-                                               dest[i++]=dest[idx-1];
-                                               dest[i++]=dest[idx-1];
-                                               dest[i++]=dest[idx-1];
-                                               break;
-                                       default:        // this shouldn't happen, don't stuff any bits
-                                               break;
-                               }
-                               n=0;
-                               lastval=dest[idx];
-                       }
-               }
-               m=i;
+               // 1->0 : fc/8 in sets of 6
+               // 0->1 : fc/10 in sets of 5
+               size = aggregate_bits(dest,size, 6,5,5);
+

                WDT_HIT();
 
                // final loop, go over previously decoded manchester data and decode into usable tag ID
                // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
                WDT_HIT();
 
                // final loop, go over previously decoded manchester data and decode into usable tag ID
                // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0

-               for( idx=0; idx<m-6; idx++) {
+               uint8_t frame_marker_mask[] = {1,1,1,0,0,0};
+               int numshifts = 0;
+               idx = 0;
+               while( idx + sizeof(frame_marker_mask) < size) {

                        // search for a start of frame marker
                        // search for a start of frame marker

-                       if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
-                       {
-                               found=1;
-                               idx+=6;
-        if (found && (hi2|hi|lo)) {
-          if (hi2 != 0){
-            Dbprintf("TAG ID: %x%08x%08x (%d)",
-                     (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-          }
-          else {
-            Dbprintf("TAG ID: %x%08x (%d)",
-                     (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-          }
-                                       /* if we're only looking for one tag */
-                                       if (findone)
-                                       {
-                                               *high = hi;
-                                               *low = lo;
-                                               return;
-                                       }
-          hi2=0;
-                                       hi=0;
-                                       lo=0;
-                                       found=0;
-                               }
-                       }
-                       if (found) {
-                               if (dest[idx] && (!dest[idx+1]) ) {
+                       if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
+                       { // frame marker found
+                               idx+=sizeof(frame_marker_mask);
+
+                               while(dest[idx] != dest[idx+1] && idx < size-2)
+                               {       
+                                       // Keep going until next frame marker (or error)
+                                       // Shift in a bit. Start by shifting high registers

           hi2=(hi2<<1)|(hi>>31);
                                        hi=(hi<<1)|(lo>>31);
           hi2=(hi2<<1)|(hi>>31);
                                        hi=(hi<<1)|(lo>>31);

+                                       //Then, shift in a 0 or one into low
+                                       if (dest[idx] && !dest[idx+1])  // 1 0

                                        lo=(lo<<1)|0;
                                        lo=(lo<<1)|0;

-                               } else if ( (!dest[idx]) && dest[idx+1]) {
-          hi2=(hi2<<1)|(hi>>31);
-                                       hi=(hi<<1)|(lo>>31);
-                                       lo=(lo<<1)|1;
-                               } else {
-                                       found=0;
-          hi2=0;
-                                       hi=0;
-                                       lo=0;
+                                       else // 0 1
+                                               lo=(lo<<1)|
+                                                               1;
+                                       numshifts ++;
+                                       idx += 2;

                                }
                                }

-                               idx++;
-                       }
-                       if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
-                       {
-                               found=1;
-                               idx+=6;
-                               if (found && (hi|lo)) {
-          if (hi2 != 0){
-            Dbprintf("TAG ID: %x%08x%08x (%d)",
-                     (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-          }
-          else {
-            Dbprintf("TAG ID: %x%08x (%d)",
-                     (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-          }
-                                       /* if we're only looking for one tag */
-                                       if (findone)
-                                       {
-                                               *high = hi;
-                                               *low = lo;
-                                               return;
+                               //Dbprintf("Num shifts: %d ", numshifts);
+                               // Hopefully, we read a tag and  hit upon the next frame marker
+                               if(idx + sizeof(frame_marker_mask) < size)
+                               {
+                               if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
+                               {
+                                       if (hi2 != 0){
+                                               Dbprintf("TAG ID: %x%08x%08x (%d)",
+                                                        (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+                                       }
+                                       else {
+                                               Dbprintf("TAG ID: %x%08x (%d)",
+                                                (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);

                                        }
                                        }

-          hi2=0;
-                                       hi=0;
-                                       lo=0;
-                                       found=0;

                                }
                                }

+
+                               }
+
+                               // reset
+                               hi2 = hi = lo = 0;
+                               numshifts = 0;
+                       }else
+                       {
+                               idx++;

                        }
                }
                WDT_HIT();
                        }
                }
                WDT_HIT();

+

        }
        }

+       DbpString("Stopped");
+       if (ledcontrol) LED_A_OFF();

 }
 
 }
 

-void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
+uint32_t bytebits_to_byte(uint8_t* src, int numbits)

 {
 {

-       uint8_t *dest = (uint8_t *)BigBuf;
-       int m=0, n=0, i=0, idx=0, lastval=0;
-       int found=0;
-       uint32_t code=0, code2=0;
-       //uint32_t hi2=0, hi=0, lo=0;
+       uint32_t num = 0;
+       for(int i = 0 ; i < numbits ; i++)
+       {
+               num = (num << 1) | (*src);
+               src++;
+       }
+       return num;
+}

 
 

-       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);

 
 

-       // Connect the A/D to the peak-detected low-frequency path.
-       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
+{
+       uint8_t *dest = (uint8_t *)BigBuf;

 
 

-       // Give it a bit of time for the resonant antenna to settle.
-       SpinDelay(50);
+       size_t size=0, idx=0;
+       uint32_t code=0, code2=0;

 
 

-       // Now set up the SSC to get the ADC samples that are now streaming at us.
-       FpgaSetupSsc();
+       // Configure to go in 125Khz listen mode
+       LFSetupFPGAForADC(0, true);

 
 

-       for(;;) {
+       while(!BUTTON_PRESS()) {

                WDT_HIT();
                WDT_HIT();

-               if (ledcontrol)
-                       LED_A_ON();
-               if(BUTTON_PRESS()) {
-                       DbpString("Stopped");
-                       if (ledcontrol)
-                               LED_A_OFF();
-                       return;
-               }
+               if (ledcontrol) LED_A_ON();

 
 

-               i = 0;
-               m = sizeof(BigBuf);
-               memset(dest,128,m);
-               for(;;) {
-                       if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
-                               AT91C_BASE_SSC->SSC_THR = 0x43;
-                               if (ledcontrol)
-                                       LED_D_ON();
-                       }
-                       if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
-                               dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
-                               // we don't care about actual value, only if it's more or less than a
-                               // threshold essentially we capture zero crossings for later analysis
-                               if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
-                               i++;
-                               if (ledcontrol)
-                                       LED_D_OFF();
-                               if(i >= m) {
-                                       break;
-                               }
-                       }
-               }
+               DoAcquisition125k_internal(-1,true);
+               size  = sizeof(BigBuf);

 
                // FSK demodulator
 
                // FSK demodulator

-
-               // sync to first lo-hi transition
-               for( idx=1; idx<m; idx++) {
-                       if (dest[idx-1]<dest[idx])
-                               lastval=idx;
-                               break;
-               }
-               WDT_HIT();
-
-               // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
-               // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
-               // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
-               for( i=0; idx<m; idx++) {
-                       if (dest[idx-1]<dest[idx]) {
-                               dest[i]=idx-lastval;
-                               if (dest[i] <= 8) {
-                                               dest[i]=1;
-                               } else {
-                                               dest[i]=0;
-                               }
-
-                               lastval=idx;
-                               i++;
-                       }
-               }
-               m=i;
-               WDT_HIT();
+               size = fsk_demod(dest, size);

 
                // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
 
                // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns

-               lastval=dest[0];
-               idx=0;
-               i=0;
-               n=0;
-               for( idx=0; idx<m; idx++) {
-                       if (dest[idx]==lastval) {
-                               n++;
-                       } else {
-                               // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,
-                               // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets
-                               // swallowed up by rounding
-                               // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding
-                               // special start of frame markers use invalid manchester states (no transitions) by using sequences
-                               // like 111000
-                               if (dest[idx-1]) {
-                                       n=(n+1)/7;                      // fc/8 in sets of 7
-                               } else {
-                                       n=(n+1)/6;                      // fc/10 in sets of 6
-                               }
-                               switch (n) {                    // stuff appropriate bits in buffer
-                                       case 0:
-                                       case 1: // one bit
-                                               dest[i++]=dest[idx-1]^1;
-                                               //Dbprintf("%d",dest[idx-1]);
-                                               break;
-                                       case 2: // two bits
-                                               dest[i++]=dest[idx-1]^1;
-                                               dest[i++]=dest[idx-1]^1;
-                                               //Dbprintf("%d",dest[idx-1]);
-                                               //Dbprintf("%d",dest[idx-1]);
-                                               break;
-                                       case 3: // 3 bit start of frame markers
-                                               for(int j=0; j<3; j++){
-                                                 dest[i++]=dest[idx-1]^1;
-                                               //  Dbprintf("%d",dest[idx-1]);
-                                               }
-                                               break;
-                                       case 4:
-                                               for(int j=0; j<4; j++){
-                                                 dest[i++]=dest[idx-1]^1;
-                                               //  Dbprintf("%d",dest[idx-1]);
-                                               }
-                                               break;
-                                       case 5:
-                                               for(int j=0; j<5; j++){
-                                                 dest[i++]=dest[idx-1]^1;
-                                               //  Dbprintf("%d",dest[idx-1]);
-                                               }
-                                               break;
-                                       case 6:
-                                               for(int j=0; j<6; j++){
-                                                 dest[i++]=dest[idx-1]^1;
-                                               //  Dbprintf("%d",dest[idx-1]);
-                                               }
-                                               break;
-                                       case 7:
-                                               for(int j=0; j<7; j++){
-                                                 dest[i++]=dest[idx-1]^1;
-                                               //  Dbprintf("%d",dest[idx-1]);
-                                               }
-                                               break;
-                                       case 8:
-                                               for(int j=0; j<8; j++){
-                                                 dest[i++]=dest[idx-1]^1;
-                                               //  Dbprintf("%d",dest[idx-1]);
-                                               }
-                                               break;
-                                       case 9:
-                                               for(int j=0; j<9; j++){
-                                                 dest[i++]=dest[idx-1]^1;
-                                               //  Dbprintf("%d",dest[idx-1]);
-                                               }
-                                               break;
-                                       case 10:
-                                               for(int j=0; j<10; j++){
-                                                 dest[i++]=dest[idx-1]^1;
-                                               //  Dbprintf("%d",dest[idx-1]);
-                                               }
-                                               break;
-                                       case 11:
-                                               for(int j=0; j<11; j++){
-                                                 dest[i++]=dest[idx-1]^1;
-                                               //  Dbprintf("%d",dest[idx-1]);
-                                               }
-                                               break;
-                                       case 12:
-                                               for(int j=0; j<12; j++){
-                                                 dest[i++]=dest[idx-1]^1;
-                                                // Dbprintf("%d",dest[idx-1]);
-                                               }
-                                               break;
-                                       default:        // this shouldn't happen, don't stuff any bits
-                                               //Dbprintf("%d",dest[idx-1]);
-                                               break;
-                               }
-                               n=0;
-                               lastval=dest[idx];
-                       }
-               }//end for
-               /*for(int j=0; j<64;j+=8){
-                 Dbprintf("%d%d%d%d%d%d%d%d",dest[j],dest[j+1],dest[j+2],dest[j+3],dest[j+4],dest[j+5],dest[j+6],dest[j+7]);
-               }
-               Dbprintf("\n");*/
-               m=i;
+               // 1->0 : fc/8 in sets of 7
+               // 0->1 : fc/10 in sets of 6
+               size = aggregate_bits(dest, size, 7,6,13);
+

                WDT_HIT();
                
                WDT_HIT();
                

-        for( idx=0; idx<m-9; idx++) {
-         if ( !(dest[idx]) && !(dest[idx+1]) && !(dest[idx+2]) && !(dest[idx+3]) && !(dest[idx+4]) && !(dest[idx+5]) && !(dest[idx+6]) && !(dest[idx+7]) && !(dest[idx+8])&& (dest[idx+9])){
-               found=1;
-               //idx+=9;
-               if (found) {
+               //Handle the data
+           uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1};
+               for( idx=0; idx < size - 64; idx++) {
+
+               if ( memcmp(dest + idx, mask, sizeof(mask)) ) continue;
+

                    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx],   dest[idx+1],   dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7]);
                    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+8], dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15]);                         
                    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+16],dest[idx+17],dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23]);
                    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx],   dest[idx+1],   dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7]);
                    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+8], dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15]);                         
                    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+16],dest[idx+17],dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23]);


@@ -1011,58 +824,26 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
                    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53],dest[idx+54],dest[idx+55]);
                    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
                
                    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53],dest[idx+54],dest[idx+55]);
                    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
                

-                   short version='\x00';
-                   char unknown='\x00';
-                   uint16_t number=0;
-                   for(int j=14;j<18;j++){
-                      //Dbprintf("%d",dest[idx+j]);
-                      version <<=1;
-                      if (dest[idx+j]) version |= 1;
-                   }
-                   for(int j=19;j<27;j++){
-                      //Dbprintf("%d",dest[idx+j]);
-                      unknown <<=1;
-                      if (dest[idx+j]) unknown |= 1;
-                   }
-                   for(int j=36;j<45;j++){
-                      //Dbprintf("%d",dest[idx+j]);
-                      number <<=1;
-                      if (dest[idx+j]) number |= 1;
-                   }
-                   for(int j=46;j<53;j++){
-                      //Dbprintf("%d",dest[idx+j]);
-                      number <<=1;
-                      if (dest[idx+j]) number |= 1;
-                   }
-                   for(int j=0; j<32; j++){
-                       code <<=1;
-                       if(dest[idx+j]) code |= 1;
-                   }
-                   for(int j=32; j<64; j++){
-                       code2 <<=1;
-                       if(dest[idx+j]) code2 |= 1;
-                   }
+                   code = bytebits_to_byte(dest+idx,32);
+                   code2 = bytebits_to_byte(dest+idx+32,32); 
+                       
+                   short version = bytebits_to_byte(dest+idx+14,4); 
+                   char unknown = bytebits_to_byte(dest+idx+19,8) ;
+                   uint16_t number = bytebits_to_byte(dest+idx+36,9); 

                    
                    Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,unknown,number,code,code2);
                    
                    Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,unknown,number,code,code2);

-                   if (ledcontrol)
-                       LED_D_OFF();
-               }
+                   if (ledcontrol)     LED_D_OFF();
+               

                // if we're only looking for one tag 
                if (findone){
                // if we're only looking for one tag 
                if (findone){

-                       //*high = hi;
-                       //*low = lo;

                        LED_A_OFF();
                        return;
                }
                        LED_A_OFF();
                        return;
                }

-      
-               //hi=0;
-               //lo=0;
-               found=0;
-         }
-               
-       }

        }
        WDT_HIT();
        }
        WDT_HIT();

+       }
+       DbpString("Stopped");
+       if (ledcontrol) LED_A_OFF();

 }
 
 /*------------------------------
 }
 
 /*------------------------------


@@ -1071,14 +852,14 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
  */
 
 /* T55x7 configuration register definitions */
  */
 
 /* T55x7 configuration register definitions */

-#define T55x7_POR_DELAY                        0x00000001
-#define T55x7_ST_TERMINATOR            0x00000008
-#define T55x7_PWD                      0x00000010
+#define T55x7_POR_DELAY                                0x00000001
+#define T55x7_ST_TERMINATOR                    0x00000008
+#define T55x7_PWD                                      0x00000010

 #define T55x7_MAXBLOCK_SHIFT           5
 #define T55x7_MAXBLOCK_SHIFT           5

-#define T55x7_AOR                      0x00000200
-#define T55x7_PSKCF_RF_2               0
-#define T55x7_PSKCF_RF_4               0x00000400
-#define T55x7_PSKCF_RF_8               0x00000800
+#define T55x7_AOR                                      0x00000200
+#define T55x7_PSKCF_RF_2                       0
+#define T55x7_PSKCF_RF_4                       0x00000400
+#define T55x7_PSKCF_RF_8                       0x00000800

 #define T55x7_MODULATION_DIRECT                0
 #define T55x7_MODULATION_PSK1          0x00001000
 #define T55x7_MODULATION_PSK2          0x00002000
 #define T55x7_MODULATION_DIRECT                0
 #define T55x7_MODULATION_PSK1          0x00001000
 #define T55x7_MODULATION_PSK2          0x00002000


@@ -1089,17 +870,17 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 #define T55x7_MODULATION_FSK2a         0x00007000
 #define T55x7_MODULATION_MANCHESTER    0x00008000
 #define T55x7_MODULATION_BIPHASE       0x00010000
 #define T55x7_MODULATION_FSK2a         0x00007000
 #define T55x7_MODULATION_MANCHESTER    0x00008000
 #define T55x7_MODULATION_BIPHASE       0x00010000

-#define T55x7_BITRATE_RF_8             0
-#define T55x7_BITRATE_RF_16            0x00040000
-#define T55x7_BITRATE_RF_32            0x00080000
-#define T55x7_BITRATE_RF_40            0x000C0000
-#define T55x7_BITRATE_RF_50            0x00100000
-#define T55x7_BITRATE_RF_64            0x00140000
+#define T55x7_BITRATE_RF_8                     0
+#define T55x7_BITRATE_RF_16                    0x00040000
+#define T55x7_BITRATE_RF_32                    0x00080000
+#define T55x7_BITRATE_RF_40                    0x000C0000
+#define T55x7_BITRATE_RF_50                    0x00100000
+#define T55x7_BITRATE_RF_64                    0x00140000

 #define T55x7_BITRATE_RF_100           0x00180000
 #define T55x7_BITRATE_RF_128           0x001C0000
 
 /* T5555 (Q5) configuration register definitions */
 #define T55x7_BITRATE_RF_100           0x00180000
 #define T55x7_BITRATE_RF_128           0x001C0000
 
 /* T5555 (Q5) configuration register definitions */

-#define T5555_ST_TERMINATOR            0x00000001
+#define T5555_ST_TERMINATOR                    0x00000001

 #define T5555_MAXBLOCK_SHIFT           0x00000001
 #define T5555_MODULATION_MANCHESTER    0
 #define T5555_MODULATION_PSK1          0x00000010
 #define T5555_MAXBLOCK_SHIFT           0x00000001
 #define T5555_MODULATION_MANCHESTER    0
 #define T5555_MODULATION_PSK1          0x00000010


@@ -1109,32 +890,43 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 #define T5555_MODULATION_FSK2          0x00000050
 #define T5555_MODULATION_BIPHASE       0x00000060
 #define T5555_MODULATION_DIRECT                0x00000070
 #define T5555_MODULATION_FSK2          0x00000050
 #define T5555_MODULATION_BIPHASE       0x00000060
 #define T5555_MODULATION_DIRECT                0x00000070

-#define T5555_INVERT_OUTPUT            0x00000080
-#define T5555_PSK_RF_2                 0
-#define T5555_PSK_RF_4                 0x00000100
-#define T5555_PSK_RF_8                 0x00000200
-#define T5555_USE_PWD                  0x00000400
-#define T5555_USE_AOR                  0x00000800
-#define T5555_BITRATE_SHIFT            12
-#define T5555_FAST_WRITE               0x00004000
-#define T5555_PAGE_SELECT              0x00008000
+#define T5555_INVERT_OUTPUT                    0x00000080
+#define T5555_PSK_RF_2                         0
+#define T5555_PSK_RF_4                         0x00000100
+#define T5555_PSK_RF_8                         0x00000200
+#define T5555_USE_PWD                          0x00000400
+#define T5555_USE_AOR                          0x00000800
+#define T5555_BITRATE_SHIFT                    12
+#define T5555_FAST_WRITE                       0x00004000
+#define T5555_PAGE_SELECT                      0x00008000

 
 /*
  * Relevant times in microsecond
  * To compensate antenna falling times shorten the write times
  * and enlarge the gap ones.
  */
 
 /*
  * Relevant times in microsecond
  * To compensate antenna falling times shorten the write times
  * and enlarge the gap ones.
  */

-#define START_GAP 250
-#define WRITE_GAP 160
-#define WRITE_0   144 // 192
-#define WRITE_1   400 // 432 for T55x7; 448 for E5550
+#define START_GAP 30*8 // 10 - 50fc 250
+#define WRITE_GAP 20*8 //  8 - 30fc
+#define WRITE_0   24*8 // 16 - 31fc 24fc 192
+#define WRITE_1   54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
+
+//  VALUES TAKEN FROM EM4x function: SendForward
+//  START_GAP = 440;       (55*8) cycles at 125Khz (8us = 1cycle)
+//  WRITE_GAP = 128;       (16*8)
+//  WRITE_1   = 256 32*8;  (32*8) 
+
+//  These timings work for 4469/4269/4305 (with the 55*8 above)
+//  WRITE_0 = 23*8 , 9*8  SpinDelayUs(23*8); 
+
+#define T55xx_SAMPLES_SIZE             12000 // 32 x 32 x 10  (32 bit times numofblock (7), times clock skip..)

 
 // Write one bit to card
 void T55xxWriteBit(int bit)
 {
 
 // Write one bit to card
 void T55xxWriteBit(int bit)
 {

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
-       if (bit == 0)
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
+       if (!bit)

                SpinDelayUs(WRITE_0);
        else
                SpinDelayUs(WRITE_1);
                SpinDelayUs(WRITE_0);
        else
                SpinDelayUs(WRITE_1);


@@ -1145,14 +937,11 @@ void T55xxWriteBit(int bit)
 // Write one card block in page 0, no lock
 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 {
 // Write one card block in page 0, no lock
 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 {

-       unsigned int i;
+       uint32_t i = 0;

 
 

-       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
-
-       // Give it a bit of time for the resonant antenna to settle.
-       // And for the tag to fully power up
-       SpinDelay(150);
+       // Set up FPGA, 125kHz
+       // Wait for config.. (192+8190xPOW)x8 == 67ms
+       LFSetupFPGAForADC(0, true);

 
        // Now start writting
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 
        // Now start writting
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);


@@ -1161,11 +950,11 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
        // Opcode
        T55xxWriteBit(1);
        T55xxWriteBit(0); //Page 0
        // Opcode
        T55xxWriteBit(1);
        T55xxWriteBit(0); //Page 0

-  if (PwdMode == 1){
-    // Pwd
-    for (i = 0x80000000; i != 0; i >>= 1)
-      T55xxWriteBit(Pwd & i);
-  }
+       if (PwdMode == 1){
+               // Pwd
+               for (i = 0x80000000; i != 0; i >>= 1)
+                       T55xxWriteBit(Pwd & i);
+       }

        // Lock bit
        T55xxWriteBit(0);
 
        // Lock bit
        T55xxWriteBit(0);
 


@@ -1180,7 +969,7 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
        // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
        // so wait a little more)
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
        // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
        // so wait a little more)
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

        SpinDelay(20);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 }
        SpinDelay(20);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 }


@@ -1188,26 +977,17 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
 // Read one card block in page 0
 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 {
 // Read one card block in page 0
 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 {

-       uint8_t *dest = (uint8_t *)BigBuf;
-       int m=0, i=0;
-  
-       m = sizeof(BigBuf);
-  // Clear destination buffer before sending the command
-       memset(dest, 128, m);
-       // Connect the A/D to the peak-detected low-frequency path.
-       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
-       // Now set up the SSC to get the ADC samples that are now streaming at us.
-       FpgaSetupSsc();
-  
-       LED_D_ON();
-       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
-  
-       // Give it a bit of time for the resonant antenna to settle.
-       // And for the tag to fully power up
-       SpinDelay(150);
-  
-       // Now start writting
+       uint8_t *dest =  mifare_get_bigbufptr();
+       uint16_t bufferlength = T55xx_SAMPLES_SIZE;
+       uint32_t i = 0;
+
+       // Clear destination buffer before sending the command  0x80 = average.
+       memset(dest, 0x80, bufferlength);
+
+       // Set up FPGA, 125kHz
+       // Wait for config.. (192+8190xPOW)x8 == 67ms
+       LFSetupFPGAForADC(0, true);
+

        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        SpinDelayUs(START_GAP);
   
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        SpinDelayUs(START_GAP);
   


@@ -1225,53 +1005,40 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
        for (i = 0x04; i != 0; i >>= 1)
                T55xxWriteBit(Block & i);
   
        for (i = 0x04; i != 0; i >>= 1)
                T55xxWriteBit(Block & i);
   

-  // Turn field on to read the response
-       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       // Turn field on to read the response
+       TurnReadLFOn();

   
        // Now do the acquisition
        i = 0;
        for(;;) {
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
                        AT91C_BASE_SSC->SSC_THR = 0x43;
   
        // Now do the acquisition
        i = 0;
        for(;;) {
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
                        AT91C_BASE_SSC->SSC_THR = 0x43;

+                       LED_D_ON();

                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

-                       // we don't care about actual value, only if it's more or less than a
-                       // threshold essentially we capture zero crossings for later analysis
-      //                       if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
-                       i++;
-                       if (i >= m) break;
+                       ++i;
+                       LED_D_OFF();
+                       if (i > bufferlength) break;

                }
        }
                }
        }

-  
-  FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+ 
+       cmd_send(CMD_ACK,0,0,0,0,0);
+    FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

        LED_D_OFF();
        LED_D_OFF();

-       DbpString("DONE!");

 }
 
 // Read card traceability data (page 1)
 void T55xxReadTrace(void){
 }
 
 // Read card traceability data (page 1)
 void T55xxReadTrace(void){

-       uint8_t *dest = (uint8_t *)BigBuf;
-       int m=0, i=0;
-  
-       m = sizeof(BigBuf);
-  // Clear destination buffer before sending the command
-       memset(dest, 128, m);
-       // Connect the A/D to the peak-detected low-frequency path.
-       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
-       // Now set up the SSC to get the ADC samples that are now streaming at us.
-       FpgaSetupSsc();
-  
-       LED_D_ON();
-       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       uint8_t *dest =  mifare_get_bigbufptr();
+       uint16_t bufferlength = T55xx_SAMPLES_SIZE;
+       int i=0;
+       
+       // Clear destination buffer before sending the command 0x80 = average
+       memset(dest, 0x80, bufferlength);  

   
   

-       // Give it a bit of time for the resonant antenna to settle.
-       // And for the tag to fully power up
-       SpinDelay(150);
+       LFSetupFPGAForADC(0, true);

   
   

-       // Now start writting

        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        SpinDelayUs(START_GAP);
   
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        SpinDelayUs(START_GAP);
   


@@ -1279,26 +1046,35 @@ void T55xxReadTrace(void){
        T55xxWriteBit(1);
        T55xxWriteBit(1); //Page 1
   
        T55xxWriteBit(1);
        T55xxWriteBit(1); //Page 1
   

-  // Turn field on to read the response
-       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       // Turn field on to read the response
+       TurnReadLFOn();

   
        // Now do the acquisition
   
        // Now do the acquisition

-       i = 0;

        for(;;) {
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
                        AT91C_BASE_SSC->SSC_THR = 0x43;
        for(;;) {
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
                        AT91C_BASE_SSC->SSC_THR = 0x43;

+                       LED_D_ON();

                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

-                       i++;
-                       if (i >= m) break;
+                       ++i;
+                       LED_D_OFF();
+               
+                       if (i >= bufferlength) break;

                }
        }
   
                }
        }
   

-  FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+       cmd_send(CMD_ACK,0,0,0,0,0);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

        LED_D_OFF();
        LED_D_OFF();

-       DbpString("DONE!");
+}
+
+void TurnReadLFOn(){
+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
+       // Give it a bit of time for the resonant antenna to settle.
+       //SpinDelay(30);
+       SpinDelayUs(8*150);

 }
 
 /*-------------- Cloning routines -----------*/
 }
 
 /*-------------- Cloning routines -----------*/


@@ -1414,7 +1190,7 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
   }
   
        // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
   }
   
        // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)

-       T55xxWriteBlock(T55x7_BITRATE_RF_50    |
+       T55xxWriteBlock(T55x7_BITRATE_RF_50  |

                   T55x7_MODULATION_FSK2a |
                   last_block << T55x7_MAXBLOCK_SHIFT,
                   0,0,0);
                   T55x7_MODULATION_FSK2a |
                   last_block << T55x7_MAXBLOCK_SHIFT,
                   0,0,0);


@@ -1557,7 +1333,6 @@ void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
 // Clone Indala 64-bit tag by UID to T55x7
 void CopyIndala64toT55x7(int hi, int lo)
 {
 // Clone Indala 64-bit tag by UID to T55x7
 void CopyIndala64toT55x7(int hi, int lo)
 {

-

        //Program the 2 data blocks for supplied 64bit UID
        // and the block 0 for Indala64 format
        T55xxWriteBlock(hi,1,0,0);
        //Program the 2 data blocks for supplied 64bit UID
        // and the block 0 for Indala64 format
        T55xxWriteBlock(hi,1,0,0);


@@ -1568,15 +1343,13 @@ void CopyIndala64toT55x7(int hi, int lo)
                        2 << T55x7_MAXBLOCK_SHIFT,
                        0, 0, 0);
        //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
                        2 << T55x7_MAXBLOCK_SHIFT,
                        0, 0, 0);
        //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)

-//     T5567WriteBlock(0x603E1042,0);
+       //      T5567WriteBlock(0x603E1042,0);

 
        DbpString("DONE!");
 
        DbpString("DONE!");

-

 }      
 
 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
 {
 }      
 
 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
 {

-

        //Program the 7 data blocks for supplied 224bit UID
        // and the block 0 for Indala224 format
        T55xxWriteBlock(uid1,1,0,0);
        //Program the 7 data blocks for supplied 224bit UID
        // and the block 0 for Indala224 format
        T55xxWriteBlock(uid1,1,0,0);


@@ -1592,10 +1365,9 @@ void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int
                        7 << T55x7_MAXBLOCK_SHIFT,
                        0,0,0);
        //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
                        7 << T55x7_MAXBLOCK_SHIFT,
                        0,0,0);
        //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)

-//     T5567WriteBlock(0x603E10E2,0);
+       //      T5567WriteBlock(0x603E10E2,0);

 
        DbpString("DONE!");
 
        DbpString("DONE!");

-

 }
 
 
 }
 
 


@@ -1742,7 +1514,6 @@ int IsBlock1PCF7931(uint8_t *Block) {
        
        return 0;
 }
        
        return 0;
 }

-

 #define ALLOC 16
 
 void ReadPCF7931() {
 #define ALLOC 16
 
 void ReadPCF7931() {


@@ -1970,8 +1741,9 @@ void SendForward(uint8_t fwd_bit_count) {
   LED_D_ON();
   
   //Field on
   LED_D_ON();
   
   //Field on

+  FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

   
   // Give it a bit of time for the resonant antenna to settle.
   // And for the tag to fully power up
   
   // Give it a bit of time for the resonant antenna to settle.
   // And for the tag to fully power up


@@ -1983,7 +1755,7 @@ void SendForward(uint8_t fwd_bit_count) {
   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
   SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
   SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on

   SpinDelayUs(16*8); //16 cycles on (8us each)
   
   // now start writting
   SpinDelayUs(16*8); //16 cycles on (8us each)
   
   // now start writting


@@ -1995,12 +1767,13 @@ void SendForward(uint8_t fwd_bit_count) {
       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
       SpinDelayUs(23*8); //16-4 cycles off (8us each)
       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
       SpinDelayUs(23*8); //16-4 cycles off (8us each)
       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-      FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
+      FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on

       SpinDelayUs(9*8); //16 cycles on (8us each)
     }
   }
 }
 
       SpinDelayUs(9*8); //16 cycles on (8us each)
     }
   }
 }
 

+

 void EM4xLogin(uint32_t Password) {
   
   uint8_t fwd_bit_count;
 void EM4xLogin(uint32_t Password) {
   
   uint8_t fwd_bit_count;


@@ -2018,41 +1791,48 @@ void EM4xLogin(uint32_t Password) {
 
 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
   
 
 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
   

-  uint8_t fwd_bit_count;
-  uint8_t *dest = (uint8_t *)BigBuf;
-  int m=0, i=0;
+       uint8_t *dest =  mifare_get_bigbufptr();
+       uint16_t bufferlength = 12000;
+       uint32_t i = 0;
+
+       // Clear destination buffer before sending the command  0x80 = average.
+       memset(dest, 0x80, bufferlength);
+       
+       uint8_t fwd_bit_count;

   
   

-  //If password mode do login
-  if (PwdMode == 1) EM4xLogin(Pwd);
+       //If password mode do login
+       if (PwdMode == 1) EM4xLogin(Pwd);

   
   

-  forward_ptr = forwardLink_data;
-  fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
-  fwd_bit_count += Prepare_Addr( Address );
+       forward_ptr = forwardLink_data;
+       fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
+       fwd_bit_count += Prepare_Addr( Address );

   
   

-  m = sizeof(BigBuf);
-  // Clear destination buffer before sending the command
-  memset(dest, 128, m);
-  // Connect the A/D to the peak-detected low-frequency path.
-  SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
-  // Now set up the SSC to get the ADC samples that are now streaming at us.
-  FpgaSetupSsc();
+       // Connect the A/D to the peak-detected low-frequency path.
+       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+       // Now set up the SSC to get the ADC samples that are now streaming at us.
+       FpgaSetupSsc();

   
   

-  SendForward(fwd_bit_count);
+       SendForward(fwd_bit_count);

   
   

-  // Now do the acquisition
-  i = 0;
-  for(;;) {
-    if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
-      AT91C_BASE_SSC->SSC_THR = 0x43;
-    }
-    if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
-      dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
-      i++;
-      if (i >= m) break;
-    }
-  }
-  FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
-  LED_D_OFF();
+       // // Turn field on to read the response
+       // TurnReadLFOn();
+       
+       // Now do the acquisition
+       i = 0;
+       for(;;) {
+               if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
+                       AT91C_BASE_SSC->SSC_THR = 0x43;
+               }
+               if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
+                       dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
+                       ++i;
+                       if (i >= bufferlength) break;
+               }
+       }
+  
+       cmd_send(CMD_ACK,0,0,0,0,0);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+       LED_D_OFF();

 }
 
 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
 }
 
 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {