CHG: this timing should be quite good. needs to be verified.

[proxmark3-svn] / armsrc / lfops.c

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index 294bfb5e4206bbe36d32675d1442aea775ca95c3..aa7a9419971e25b1af971159a77929f460caf804 100644 (file)
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -19,11 +19,18 @@
 #include "protocols.h"
 #include "usb_cdc.h" // for usb_poll_validate_length
 
 #include "protocols.h"
 #include "usb_cdc.h" // for usb_poll_validate_length
 

+#ifndef SHORT_COIL
+# define SHORT_COIL()  LOW(GPIO_SSC_DOUT)
+#endif
+#ifndef OPEN_COIL
+# define OPEN_COIL()   HIGH(GPIO_SSC_DOUT)
+#endif
+

 /**
  * Function to do a modulation and then get samples.
  * @param delay_off
 /**
  * Function to do a modulation and then get samples.
  * @param delay_off

- * @param period_0
- * @param period_1
+ * @param periods  0xFFFF0000 is period_0,  0x0000FFFF is period_1
+ * @param useHighFreg

  * @param command
  */
 void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint32_t useHighFreq, uint8_t *command)
  * @param command
  */
 void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint32_t useHighFreq, uint8_t *command)


@@ -37,7 +44,7 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3
        uint16_t period_1 =  periods & 0xFFFF;
        
        // 95 == 125 KHz  88 == 124.8 KHz
        uint16_t period_1 =  periods & 0xFFFF;
        
        // 95 == 125 KHz  88 == 124.8 KHz

-       int divisor_used = (useHighFreq) ? 88 : 95 ; // 125 KHz
+       int divisor_used = (useHighFreq) ? 88 : 95;

        sample_config sc = { 0,0,1, divisor_used, 0};
        setSamplingConfig(&sc);
 
        sample_config sc = { 0,0,1, divisor_used, 0};
        setSamplingConfig(&sc);
 


@@ -59,13 +66,13 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3
                FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
                LED_D_ON();
                if(*(command++) == '0')
                FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
                LED_D_ON();
                if(*(command++) == '0')

-                       SpinDelayUs(period_0);
+                       SpinDelayUs(period_0);  // ICEMAN:  problem with (us) clock is  21.3us increments

                else
                else

-                       SpinDelayUs(period_1);
+                       SpinDelayUs(period_1);  // ICEMAN:  problem with (us) clock is  21.3us increments

        }
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        LED_D_OFF();
        }
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        LED_D_OFF();

-       SpinDelayUs(delay_off);
+       SpinDelayUs(delay_off); // ICEMAN:  problem with (us) clock is  21.3us increments

        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 


@@ -221,17 +228,17 @@ void WriteTIbyte(uint8_t b)
                if (b&(1<<i)) {
                        // stop modulating antenna
                        LOW(GPIO_SSC_DOUT);
                if (b&(1<<i)) {
                        // stop modulating antenna
                        LOW(GPIO_SSC_DOUT);

-                       SpinDelayUs(1000);
+                       SpinDelayUs(1000);      // ICEMAN:  problem with (us) clock is  21.3us increments

                        // modulate antenna
                        HIGH(GPIO_SSC_DOUT);
                        // modulate antenna
                        HIGH(GPIO_SSC_DOUT);

-                       SpinDelayUs(1000);
+                       SpinDelayUs(1000);      // ICEMAN:  problem with (us) clock is  21.3us increments

                } else {
                        // stop modulating antenna
                        LOW(GPIO_SSC_DOUT);
                } else {
                        // stop modulating antenna
                        LOW(GPIO_SSC_DOUT);

-                       SpinDelayUs(300);
+                       SpinDelayUs(300);       // ICEMAN:  problem with (us) clock is  21.3us increments

                        // modulate antenna
                        HIGH(GPIO_SSC_DOUT);
                        // modulate antenna
                        HIGH(GPIO_SSC_DOUT);

-                       SpinDelayUs(1700);
+                       SpinDelayUs(1700);      // ICEMAN:  problem with (us) clock is  21.3us increments

                }
        }
 }
                }
        }
 }


@@ -383,31 +390,30 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
 
 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 {
 
 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 {

-       int i;
+       int i = 0;

        uint8_t *tab = BigBuf_get_addr();
 
        uint8_t *tab = BigBuf_get_addr();
 

-       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);

 
        AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
        AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
        AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
 
 
        AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
        AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
        AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
 

- #define SHORT_COIL()  LOW(GPIO_SSC_DOUT)
- #define OPEN_COIL()   HIGH(GPIO_SSC_DOUT)
-
-       i = 0;

        for(;;) {
        for(;;) {

+               WDT_HIT();
+
+               if (ledcontrol) LED_D_ON();
+                               

                //wait until SSC_CLK goes HIGH
                while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
                //wait until SSC_CLK goes HIGH
                while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {

-                       if(BUTTON_PRESS() || usb_poll_validate_length() ) {
-                               DbpString("Stopped");
-                               return;
-                       }

                        WDT_HIT();
                        WDT_HIT();

+                       if ( usb_poll_validate_length() || BUTTON_PRESS() ) {
+                               FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+                               LED_D_OFF();
+                               return;                         
+                       }

                }
                }

-               if (ledcontrol) LED_D_ON();
-
+               

                if(tab[i])
                        OPEN_COIL();
                else
                if(tab[i])
                        OPEN_COIL();
                else


@@ -417,20 +423,21 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
                
                //wait until SSC_CLK goes LOW
                while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
                
                //wait until SSC_CLK goes LOW
                while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {

-                       if( BUTTON_PRESS() || usb_poll_validate_length() ) {
-                               DbpString("Stopped");
-                               return;
-                       }

                        WDT_HIT();
                        WDT_HIT();

+                       if ( usb_poll_validate_length() || BUTTON_PRESS() ) {
+                               FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+                               LED_D_OFF();
+                               return;                         
+                       }

                }
 
                i++;
                if(i == period) {
                }
 
                i++;
                if(i == period) {

-

                        i = 0;
                        if (gap) {
                        i = 0;
                        if (gap) {

+                               WDT_HIT();

                                SHORT_COIL();
                                SHORT_COIL();

-                               SpinDelayUs(gap);
+                               SpinDelayUs(gap);       // ICEMAN:  problem with (us) clock is  21.3us increments

                        }
                }
        }
                        }
                }
        }


@@ -524,7 +531,10 @@ static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
 // simulate a HID tag until the button is pressed
 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 {
 // simulate a HID tag until the button is pressed
 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 {

-       int n=0, i=0;
+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+       set_tracing(FALSE);
+               
+       int n = 0, i = 0;

        /*
         HID tag bitstream format
         The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
        /*
         HID tag bitstream format
         The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits


@@ -535,7 +545,7 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
         nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
        */
 
         nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
        */
 

-       if (hi>0xFFF) {
+       if (hi > 0xFFF) {

                DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
                return;
        }
                DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
                return;
        }


@@ -567,7 +577,8 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
                        fc(8,  &n); fc(10, &n);         // high-low transition
                }
        }
                        fc(8,  &n); fc(10, &n);         // high-low transition
                }
        }

-
+       WDT_HIT();
+       

        if (ledcontrol) LED_A_ON();
        SimulateTagLowFrequency(n, 0, ledcontrol);
        if (ledcontrol) LED_A_OFF();
        if (ledcontrol) LED_A_ON();
        SimulateTagLowFrequency(n, 0, ledcontrol);
        if (ledcontrol) LED_A_OFF();


@@ -578,8 +589,14 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
 {
 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
 {

-       int ledcontrol=1;
-       int n=0, i=0;
+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+
+       // free eventually allocated BigBuf memory
+       BigBuf_free(); BigBuf_Clear_ext(false);
+       clear_trace();
+       set_tracing(FALSE);
+       
+       int ledcontrol = 1, n = 0, i = 0;

        uint8_t fcHigh = arg1 >> 8;
        uint8_t fcLow = arg1 & 0xFF;
        uint16_t modCnt = 0;
        uint8_t fcHigh = arg1 >> 8;
        uint8_t fcLow = arg1 & 0xFF;
        uint16_t modCnt = 0;


@@ -587,13 +604,15 @@ void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
        uint8_t invert = (arg2 >> 8) & 1;
 
        for (i=0; i<size; i++){
        uint8_t invert = (arg2 >> 8) & 1;
 
        for (i=0; i<size; i++){

-               if (BitStream[i] == invert){
+               
+               if (BitStream[i] == invert)

                        fcAll(fcLow, &n, clk, &modCnt);
                        fcAll(fcLow, &n, clk, &modCnt);

-               } else {
+               else

                        fcAll(fcHigh, &n, clk, &modCnt);
                        fcAll(fcHigh, &n, clk, &modCnt);

-               }

        }
        }

-       Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
+       WDT_HIT();
+       
+       Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d", fcHigh, fcLow, clk, invert, n);

 
        if (ledcontrol) LED_A_ON();
        SimulateTagLowFrequency(n, 0, ledcontrol);
 
        if (ledcontrol) LED_A_ON();
        SimulateTagLowFrequency(n, 0, ledcontrol);


@@ -644,19 +663,21 @@ static void stAskSimBit(int *n, uint8_t clock) {
 // args clock, ask/man or askraw, invert, transmission separator
 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
 {
 // args clock, ask/man or askraw, invert, transmission separator
 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
 {

-       int ledcontrol = 1;
-       int n=0, i=0;
+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);   
+       set_tracing(FALSE);
+       
+       int ledcontrol = 1, n = 0, i = 0;

        uint8_t clk = (arg1 >> 8) & 0xFF;
        uint8_t encoding = arg1 & 0xFF;
        uint8_t separator = arg2 & 1;
        uint8_t invert = (arg2 >> 8) & 1;
 
        uint8_t clk = (arg1 >> 8) & 0xFF;
        uint8_t encoding = arg1 & 0xFF;
        uint8_t separator = arg2 & 1;
        uint8_t invert = (arg2 >> 8) & 1;
 

-       if (encoding==2){  //biphase
-               uint8_t phase=0;
+       if (encoding == 2){  //biphase
+               uint8_t phase = 0;

                for (i=0; i<size; i++){
                        biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
                }
                for (i=0; i<size; i++){
                        biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
                }

-               if (phase==1) { //run a second set inverted to keep phase in check
+               if (phase == 1) { //run a second set inverted to keep phase in check

                        for (i=0; i<size; i++){
                                biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
                        }
                        for (i=0; i<size; i++){
                                biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
                        }


@@ -676,6 +697,8 @@ void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
        else if (separator==1)
                Dbprintf("sorry but separator option not yet available");
 
        else if (separator==1)
                Dbprintf("sorry but separator option not yet available");
 

+       WDT_HIT();
+       

        Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
 
        if (ledcontrol) LED_A_ON();
        Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
 
        if (ledcontrol) LED_A_ON();


@@ -709,8 +732,10 @@ static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, b
 // args clock, carrier, invert,
 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
 {
 // args clock, carrier, invert,
 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
 {

-       int ledcontrol = 1;
-       int n=0, i=0;
+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);   
+       set_tracing(FALSE);
+       
+       int ledcontrol = 1, n = 0, i = 0;

        uint8_t clk = arg1 >> 8;
        uint8_t carrier = arg1 & 0xFF;
        uint8_t invert = arg2 & 0xFF;
        uint8_t clk = arg1 >> 8;
        uint8_t carrier = arg1 & 0xFF;
        uint8_t invert = arg2 & 0xFF;


@@ -722,6 +747,9 @@ void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
                        pskSimBit(carrier, &n, clk, &curPhase, TRUE);
                }
        }
                        pskSimBit(carrier, &n, clk, &curPhase, TRUE);
                }
        }

+       
+       WDT_HIT();
+       

        Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
                   
        if (ledcontrol) LED_A_ON();
        Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
                   
        if (ledcontrol) LED_A_ON();


@@ -1088,7 +1116,7 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
  * Q5 tags seems to have issues when these values changes. 
  */
 
  * Q5 tags seems to have issues when these values changes. 
  */
 

-#define START_GAP 31*8 // was 250 // SPEC:  1*8 to 50*8 - typ 15*8 (or 15fc)
+#define START_GAP 50*8 // was 250 // SPEC:  1*8 to 50*8 - typ 15*8 (or 15fc)

 #define WRITE_GAP 20*8 // was 160 // SPEC:  1*8 to 20*8 - typ 10*8 (or 10fc)
 #define WRITE_0   18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
 #define WRITE_1   50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc)  432 for T55x7; 448 for E5550
 #define WRITE_GAP 20*8 // was 160 // SPEC:  1*8 to 20*8 - typ 10*8 (or 10fc)
 #define WRITE_0   18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
 #define WRITE_1   50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc)  432 for T55x7; 448 for E5550


@@ -1116,7 +1144,7 @@ void TurnReadLFOn(int delay) {
        //int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
        // where to save it
        
        //int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
        // where to save it
        

-       SpinDelayUs(delay);
+       SpinDelayUs(delay);     // ICEMAN:  problem with (us) clock is  21.3us increments

 }
 
 // Write one bit to card
 }
 
 // Write one bit to card


@@ -1126,7 +1154,7 @@ void T55xxWriteBit(int bit) {
        else
                TurnReadLFOn(WRITE_1);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        else
                TurnReadLFOn(WRITE_1);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

-       SpinDelayUs(WRITE_GAP);
+       SpinDelayUs(WRITE_GAP); // ICEMAN:  problem with (us) clock is  21.3us increments

 }
 
 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
 }
 
 // Send T5577 reset command then read stream (see if we can identify the start of the stream)


@@ -1140,7 +1168,7 @@ void T55xxResetRead(void) {
 
        // Trigger T55x7 in mode.
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 
        // Trigger T55x7 in mode.
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

-       SpinDelayUs(START_GAP);
+       SpinDelayUs(START_GAP); // ICEMAN:  problem with (us) clock is  21.3us increments

 
        // reset tag - op code 00
        T55xxWriteBit(0);
 
        // reset tag - op code 00
        T55xxWriteBit(0);


@@ -1170,7 +1198,7 @@ void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg)
        
        // Trigger T55x7 in mode.
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        
        // Trigger T55x7 in mode.
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

-       SpinDelayUs(START_GAP);
+       SpinDelayUs(START_GAP); // ICEMAN:  problem with (us) clock is  21.3us increments

 
        // Opcode 10
        T55xxWriteBit(1);
 
        // Opcode 10
        T55xxWriteBit(1);


@@ -1219,17 +1247,18 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
        bool RegReadMode = (Block == 0xFF);
        
        //clear buffer now so it does not interfere with timing later
        bool RegReadMode = (Block == 0xFF);
        
        //clear buffer now so it does not interfere with timing later

-       BigBuf_Clear_ext(false);
+       BigBuf_Clear_keep_EM();

 
        //make sure block is at max 7
        Block &= 0x7;
 
        // Set up FPGA, 125kHz to power up the tag
        LFSetupFPGAForADC(95, true);
 
        //make sure block is at max 7
        Block &= 0x7;
 
        // Set up FPGA, 125kHz to power up the tag
        LFSetupFPGAForADC(95, true);

+       SpinDelay(3);

        
        // Trigger T55x7 Direct Access Mode with start gap
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        
        // Trigger T55x7 Direct Access Mode with start gap
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

-       SpinDelayUs(START_GAP);
+       SpinDelayUs(START_GAP); // ICEMAN:  problem with (us) clock is  21.3us increments

        
        // Opcode 1[page]
        T55xxWriteBit(1);
        
        // Opcode 1[page]
        T55xxWriteBit(1);


@@ -1245,8 +1274,8 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
        
        // Send Block number (if direct access mode)
        if (!RegReadMode)
        
        // Send Block number (if direct access mode)
        if (!RegReadMode)

-       for (i = 0x04; i != 0; i >>= 1)
-               T55xxWriteBit(Block & i);
+               for (i = 0x04; i != 0; i >>= 1)
+                       T55xxWriteBit(Block & i);

 
        // Turn field on to read the response
        TurnReadLFOn(READ_GAP);
 
        // Turn field on to read the response
        TurnReadLFOn(READ_GAP);


@@ -1269,7 +1298,7 @@ void T55xxWakeUp(uint32_t Pwd){
        
        // Trigger T55x7 Direct Access Mode
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        
        // Trigger T55x7 Direct Access Mode
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

-       SpinDelayUs(START_GAP);
+       SpinDelayUs(START_GAP); // ICEMAN:  problem with (us) clock is  21.3us increments

        
        // Opcode 10
        T55xxWriteBit(1);
        
        // Opcode 10
        T55xxWriteBit(1);


@@ -1600,20 +1629,20 @@ void SendForward(uint8_t fwd_bit_count) {
        fwd_bit_sz--; //prepare next bit modulation
        fwd_write_ptr++;
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
        fwd_bit_sz--; //prepare next bit modulation
        fwd_write_ptr++;
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

-       SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
+       SpinDelayUs(55*8); //55 cycles off (8us each)for 4305   // ICEMAN:  problem with (us) clock is  21.3us increments

        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on

-       SpinDelayUs(16*8); //16 cycles on (8us each)
+       SpinDelayUs(16*8); //16 cycles on (8us each)    // ICEMAN:  problem with (us) clock is  21.3us increments

 
        // now start writting
        while(fwd_bit_sz-- > 0) { //prepare next bit modulation
                if(((*fwd_write_ptr++) & 1) == 1)
 
        // now start writting
        while(fwd_bit_sz-- > 0) { //prepare next bit modulation
                if(((*fwd_write_ptr++) & 1) == 1)

-                       SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
+                       SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)     // ICEMAN:  problem with (us) clock is  21.3us increments

                else {
                        //These timings work for 4469/4269/4305 (with the 55*8 above)
                        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
                else {
                        //These timings work for 4469/4269/4305 (with the 55*8 above)
                        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

-                       SpinDelayUs(23*8); //16-4 cycles off (8us each)
+                       SpinDelayUs(23*8); //16-4 cycles off (8us each) // ICEMAN:  problem with (us) clock is  21.3us increments

                        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
                        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on

-                       SpinDelayUs(9*8); //16 cycles on (8us each)
+                       SpinDelayUs(9*8); //16 cycles on (8us each)     // ICEMAN:  problem with (us) clock is  21.3us increments

                }
        }
 }
                }
        }
 }