Cleanup Code

[proxmark3-svn] / armsrc / fpgaloader.c

diff --git a/armsrc/fpgaloader.c b/armsrc/fpgaloader.c
index 7e6845fdc67bf9d3b3a61ab34badbfad1fae7ed6..5ca0cce157e75167eb2926b6885497879b5b9ca3 100644 (file)
--- a/armsrc/fpgaloader.c
+++ b/armsrc/fpgaloader.c
@@ -9,23 +9,30 @@
 // Routines to load the FPGA image, and then to configure the FPGA's major
 // mode once it is configured.
 //-----------------------------------------------------------------------------
 // Routines to load the FPGA image, and then to configure the FPGA's major
 // mode once it is configured.
 //-----------------------------------------------------------------------------

-#include "proxmark3.h"
+
+#include "fpgaloader.h"
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>

 #include "apps.h"
 #include "apps.h"

+#include "fpga.h"
+#include "proxmark3.h"

 #include "util.h"
 #include "string.h"
 #include "util.h"
 #include "string.h"

+#include "BigBuf.h"
+#include "zlib.h"

 
 // remember which version of the bitstream we have already downloaded to the FPGA
 
 // remember which version of the bitstream we have already downloaded to the FPGA

-static int downloaded_bitstream = FPGA_BITSTREAM_ERR;
+static int downloaded_bitstream = 0;

 
 // this is where the bitstreams are located in memory:
 
 // this is where the bitstreams are located in memory:

-extern uint8_t _binary_fpga_lf_bit_start, _binary_fpga_lf_bit_end;
-extern uint8_t _binary_fpga_hf_bit_start, _binary_fpga_hf_bit_end;
+extern uint8_t _binary_obj_fpga_all_bit_z_start, _binary_obj_fpga_all_bit_z_end;
+

 static uint8_t *fpga_image_ptr = NULL;
 static uint8_t *fpga_image_ptr = NULL;

+static uint32_t uncompressed_bytes_cnt;

 
 

-static const uint8_t _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};
-static const uint8_t _gzip_header[] = {0x1f, 0x8b, 0x08};  // including compression method 0x08 (deflate)
-#define GZIP_HEADER_SIZE               sizeof(_gzip_header)
-#define FPGA_BITSTREAM_FIXED_HEADER_SIZE       sizeof(_bitparse_fixed_header)
+#define OUTPUT_BUFFER_LEN              80

 
 //-----------------------------------------------------------------------------
 // Set up the Serial Peripheral Interface as master
 
 //-----------------------------------------------------------------------------
 // Set up the Serial Peripheral Interface as master


@@ -105,10 +112,10 @@ void SetupSpi(int mode)
 }
 
 //-----------------------------------------------------------------------------
 }
 
 //-----------------------------------------------------------------------------

-// Set up the synchronous serial port, with the one set of options that we
-// always use when we are talking to the FPGA. Both RX and TX are enabled.
+// Set up the synchronous serial port with the set of options that fits
+// the FPGA mode. Both RX and TX are always enabled.

 //-----------------------------------------------------------------------------
 //-----------------------------------------------------------------------------

-void FpgaSetupSsc(void)
+void FpgaSetupSsc(uint8_t FPGA_mode)

 {
        // First configure the GPIOs, and get ourselves a clock.
        AT91C_BASE_PIOA->PIO_ASR =
 {
        // First configure the GPIOs, and get ourselves a clock.
        AT91C_BASE_PIOA->PIO_ASR =


@@ -123,17 +130,21 @@ void FpgaSetupSsc(void)
        // Now set up the SSC proper, starting from a known state.
        AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
 
        // Now set up the SSC proper, starting from a known state.
        AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
 

-       // RX clock comes from TX clock, RX starts when TX starts, data changes
-       // on RX clock rising edge, sampled on falling edge
+       // RX clock comes from TX clock, RX starts on Transmit Start,
+       // data and frame signal is sampled on falling edge of RK

        AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
 
        AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
 

-       // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
+       // 8, 16 or 32 bits per transfer, no loopback, MSB first, 1 transfer per sync

        // pulse, no output sync
        // pulse, no output sync

-       AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) |     AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
+       if ((FPGA_mode & 0xe0) == FPGA_MAJOR_MODE_HF_READER && FpgaGetCurrent() == FPGA_BITSTREAM_HF) {
+               AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(16) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
+       } else {
+               AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
+       }               

 
 

-       // clock comes from TK pin, no clock output, outputs change on falling
-       // edge of TK, sample on rising edge of TK, start on positive-going edge of sync
-       AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) |   SSC_CLOCK_MODE_START(5);
+       // TX clock comes from TK pin, no clock output, outputs change on falling
+       // edge of TK, frame sync is sampled on rising edge of TK, start TX on rising edge of TF
+       AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) | SSC_CLOCK_MODE_START(5);

 
        // tx framing is the same as the rx framing
        AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;
 
        // tx framing is the same as the rx framing
        AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;


@@ -147,32 +158,103 @@ void FpgaSetupSsc(void)
 // ourselves, not to another buffer). The stuff to manipulate those buffers
 // is in apps.h, because it should be inlined, for speed.
 //-----------------------------------------------------------------------------
 // ourselves, not to another buffer). The stuff to manipulate those buffers
 // is in apps.h, because it should be inlined, for speed.
 //-----------------------------------------------------------------------------

-bool FpgaSetupSscDma(uint8_t *buf, int len)
+bool FpgaSetupSscDma(uint8_t *buf, uint16_t sample_count)
+{
+       if (buf == NULL) return false;
+
+       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;        // Disable DMA Transfer
+       AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf;           // transfer to this memory address
+       AT91C_BASE_PDC_SSC->PDC_RCR = sample_count;             // transfer this many samples
+       AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf;          // next transfer to same memory address
+       AT91C_BASE_PDC_SSC->PDC_RNCR = sample_count;            // ... with same number of samples
+       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;         // go!
+       return true;
+}
+
+
+//----------------------------------------------------------------------------
+// Uncompress (inflate) the FPGA data. Returns one decompressed byte with
+// each call. 
+//----------------------------------------------------------------------------
+static int get_from_fpga_combined_stream(z_streamp compressed_fpga_stream, uint8_t *output_buffer)
+{
+       if (fpga_image_ptr == compressed_fpga_stream->next_out) {       // need more data
+               compressed_fpga_stream->next_out = output_buffer;
+               compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
+               fpga_image_ptr = output_buffer;
+               int res = inflate(compressed_fpga_stream, Z_SYNC_FLUSH);
+               if (res != Z_OK)
+                       Dbprintf("inflate returned: %d, %s", res, compressed_fpga_stream->msg);
+
+               if (res < 0)
+                       return res;
+       }
+
+       uncompressed_bytes_cnt++;
+       
+       return *fpga_image_ptr++;
+}
+
+//----------------------------------------------------------------------------
+// Undo the interleaving of several FPGA config files. FPGA config files
+// are combined into one big file:
+// 288 bytes from FPGA file 1, followed by 288 bytes from FGPA file 2, etc.
+//----------------------------------------------------------------------------
+static int get_from_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)

 {
 {

-       if (buf == NULL) {
-        return false;
-    }
-
-       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;        // Disable DMA Transfer
-       AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf;           // transfer to this memory address
-       AT91C_BASE_PDC_SSC->PDC_RCR = len;                                      // transfer this many bytes
-       AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf;          // next transfer to same memory address
-       AT91C_BASE_PDC_SSC->PDC_RNCR = len;                                     // ... with same number of bytes
-       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;         // go!
-    
-    return true;
+       while((uncompressed_bytes_cnt / FPGA_INTERLEAVE_SIZE) % fpga_bitstream_num != (bitstream_version - 1)) {
+               // skip undesired data belonging to other bitstream_versions
+               get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
+       }
+
+       return get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
+       

 }
 
 
 }
 
 

-void reset_fpga_stream(uint8_t *image_start)
+static voidpf fpga_inflate_malloc(voidpf opaque, uInt items, uInt size)

 {
 {

-       fpga_image_ptr = image_start;
+       return BigBuf_malloc(items*size);

 }
 
 
 }
 
 

-uint8_t get_from_fpga_stream(void)
+static void fpga_inflate_free(voidpf opaque, voidpf address)

 {
 {

-       return *fpga_image_ptr++;
+       BigBuf_free(); BigBuf_Clear_ext(false);
+}
+
+
+//----------------------------------------------------------------------------
+// Initialize decompression of the respective (HF or LF) FPGA stream 
+//----------------------------------------------------------------------------
+static bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
+{
+       uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
+       
+       uncompressed_bytes_cnt = 0;
+       
+       // initialize z_stream structure for inflate:
+       compressed_fpga_stream->next_in = &_binary_obj_fpga_all_bit_z_start;
+       compressed_fpga_stream->avail_in = &_binary_obj_fpga_all_bit_z_end - &_binary_obj_fpga_all_bit_z_start;
+       compressed_fpga_stream->next_out = output_buffer;
+       compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
+       compressed_fpga_stream->zalloc = &fpga_inflate_malloc;
+       compressed_fpga_stream->zfree = &fpga_inflate_free;
+
+       inflateInit2(compressed_fpga_stream, 0);
+
+       fpga_image_ptr = output_buffer;
+
+       for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++) {
+               header[i] = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
+       }
+       
+       // Check for a valid .bit file (starts with bitparse_fixed_header)
+       if(memcmp(bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0) {
+               return true;
+       } else {
+               return false;
+       }

 }
 
 
 }
 
 


@@ -190,8 +272,11 @@ static void DownloadFPGA_byte(unsigned char w)
 }
 
 // Download the fpga image starting at current stream position with length FpgaImageLen bytes
 }
 
 // Download the fpga image starting at current stream position with length FpgaImageLen bytes

-static void DownloadFPGA(int FpgaImageLen)
+static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp compressed_fpga_stream, uint8_t *output_buffer)

 {
 {

+
+       //Dbprintf("DownloadFPGA(len: %d)", FpgaImageLen);
+       

        int i=0;
 
        AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
        int i=0;
 
        AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;


@@ -243,10 +328,15 @@ static void DownloadFPGA(int FpgaImageLen)
                return;
        }
 
                return;
        }
 

-       while(FpgaImageLen-->0) {
-               DownloadFPGA_byte(get_from_fpga_stream());
+       for(i = 0; i < FpgaImageLen; i++) {
+               int b = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
+               if (b < 0) {
+                       Dbprintf("Error %d during FpgaDownload", b);
+                       break;
+               }
+               DownloadFPGA_byte(b);

        }
        }

-
+       

        // continue to clock FPGA until ready signal goes high
        i=100000;
        while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {
        // continue to clock FPGA until ready signal goes high
        i=100000;
        while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {


@@ -269,13 +359,13 @@ static void DownloadFPGA(int FpgaImageLen)
  * (big endian), <length> bytes content. Except for section 'e' which has 4 bytes
  * length.
  */
  * (big endian), <length> bytes content. Except for section 'e' which has 4 bytes
  * length.
  */

-int bitparse_find_section(char section_name, unsigned int *section_length)
+static int bitparse_find_section(int bitstream_version, char section_name, unsigned int *section_length, z_streamp compressed_fpga_stream, uint8_t *output_buffer)

 {
        int result = 0;
        #define MAX_FPGA_BIT_STREAM_HEADER_SEARCH 100  // maximum number of bytes to search for the requested section
        uint16_t numbytes = 0;
        while(numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH) {
 {
        int result = 0;
        #define MAX_FPGA_BIT_STREAM_HEADER_SEARCH 100  // maximum number of bytes to search for the requested section
        uint16_t numbytes = 0;
        while(numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH) {

-               char current_name = get_from_fpga_stream();
+               char current_name = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);

                numbytes++;
                unsigned int current_length = 0;
                if(current_name < 'a' || current_name > 'e') {
                numbytes++;
                unsigned int current_length = 0;
                if(current_name < 'a' || current_name > 'e') {


@@ -286,12 +376,12 @@ int bitparse_find_section(char section_name, unsigned int *section_length)
                switch(current_name) {
                case 'e':
                        /* Four byte length field */
                switch(current_name) {
                case 'e':
                        /* Four byte length field */

-                       current_length += get_from_fpga_stream() << 24;
-                       current_length += get_from_fpga_stream() << 16;
+                       current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 24;
+                       current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 16;

                        numbytes += 2;
                default: /* Fall through, two byte length field */
                        numbytes += 2;
                default: /* Fall through, two byte length field */

-                       current_length += get_from_fpga_stream() << 8;
-                       current_length += get_from_fpga_stream() << 0;
+                       current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 8;
+                       current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 0;

                        numbytes += 2;
                }
 
                        numbytes += 2;
                }
 


@@ -308,7 +398,7 @@ int bitparse_find_section(char section_name, unsigned int *section_length)
                }
 
                for (uint16_t i = 0; i < current_length && numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH; i++) {
                }
 
                for (uint16_t i = 0; i < current_length && numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH; i++) {

-                       get_from_fpga_stream();
+                       get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);

                        numbytes++;
                }
        }
                        numbytes++;
                }
        }


@@ -316,124 +406,44 @@ int bitparse_find_section(char section_name, unsigned int *section_length)
        return result;
 }
 
        return result;
 }
 

-void init_fpga_inflate(void)
-{
-       // initialize zlib for inflate
-}

 
 

-
-//-----------------------------------------------------------------------------
-// Find out which FPGA image format is stored in flash, then call DownloadFPGA
-// with the right parameters to download the image
-//-----------------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Check which FPGA image is currently loaded (if any). If necessary 
+// decompress and load the correct (HF or LF) image to the FPGA
+//----------------------------------------------------------------------------

 void FpgaDownloadAndGo(int bitstream_version)
 {
 void FpgaDownloadAndGo(int bitstream_version)
 {

-       uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
+       z_stream compressed_fpga_stream;
+       uint8_t output_buffer[OUTPUT_BUFFER_LEN] = {0x00};

        
        // check whether or not the bitstream is already loaded
        
        // check whether or not the bitstream is already loaded

-       if (downloaded_bitstream == bitstream_version)
-               return;
-
-       if (bitstream_version == FPGA_BITSTREAM_LF) {
-               reset_fpga_stream(&_binary_fpga_lf_bit_start);
-       } else if (bitstream_version == FPGA_BITSTREAM_HF) {
-               reset_fpga_stream(&_binary_fpga_hf_bit_start);
-       } else
+       if (downloaded_bitstream == bitstream_version) {
+               FpgaEnableTracing();

                return;
                return;

-
-       uint16_t i = 0; 
-       for (; i < GZIP_HEADER_SIZE; i++) {
-               header[i] = get_from_fpga_stream();
-       }
-       
-       // Check for compressed new flash image format (starts with gzip header)
-       if(memcmp(_gzip_header, header, GZIP_HEADER_SIZE) == 0) {
-               init_fpga_inflate();

        }
 
        }
 

-       for (; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++) {
-               header[i] = get_from_fpga_stream();
+       // make sure that we have enough memory to decompress
+       BigBuf_free(); BigBuf_Clear_ext(false); 
+       
+       if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
+               return;

        }
 
        }
 

-       // Check for the new flash image format: Should have the .bit file at &_binary_fpga_bit_start
-       if(memcmp(_bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0) {
-               unsigned int bitstream_length;
-               if(bitparse_find_section('e', &bitstream_length)) {
-                       DownloadFPGA(bitstream_length);
-                       downloaded_bitstream = bitstream_version;
-                       return; /* All done */
-               }
+       unsigned int bitstream_length;
+       if (bitparse_find_section(bitstream_version, 'e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
+               DownloadFPGA(bitstream_version, bitstream_length, &compressed_fpga_stream, output_buffer);
+               downloaded_bitstream = bitstream_version;

        }
        }

-}      

 
 

-int FpgaGatherBitstreamVersion()
-{
-       return downloaded_bitstream;
-}
-
-void FpgaGatherVersion(int bitstream_version, char *dst, int len)
-{
-       unsigned int fpga_info_len;
-       char tempstr[40];
+       inflateEnd(&compressed_fpga_stream);

        
        

-       dst[0] = '\0';
+       // turn off antenna
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

        
        

-       if (bitstream_version == FPGA_BITSTREAM_LF) {
-               reset_fpga_stream(&_binary_fpga_lf_bit_start);
-       } else if (bitstream_version == FPGA_BITSTREAM_HF) {
-               reset_fpga_stream(&_binary_fpga_hf_bit_start);
-       } else
-               return;
-
-               
-       for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++) {
-               get_from_fpga_stream();
-       }
+       // free eventually allocated BigBuf memory
+       BigBuf_free(); BigBuf_Clear_ext(false); 
+}      

 
 

-       if(bitparse_find_section('a', &fpga_info_len)) {
-               for (uint16_t i = 0; i < fpga_info_len; i++) {
-                       char c = (char)get_from_fpga_stream();
-                       if (i < sizeof(tempstr)) {
-                               tempstr[i] = c;
-                       }
-               }
-               if (!memcmp("fpga_lf", tempstr, 7))
-                       strncat(dst, "LF ", len-1);
-               else if (!memcmp("fpga_hf", tempstr, 7))
-                       strncat(dst, "HF ", len-1);
-       }
-       strncat(dst, "FPGA image built", len-1);
-       if(bitparse_find_section('b', &fpga_info_len)) {
-               strncat(dst, " for ", len-1);
-               for (uint16_t i = 0; i < fpga_info_len; i++) {
-                       char c = (char)get_from_fpga_stream();
-                       if (i < sizeof(tempstr)) {
-                               tempstr[i] = c;
-                       }
-               }
-               strncat(dst, tempstr, len-1);
-       }
-       if(bitparse_find_section('c', &fpga_info_len)) {
-               strncat(dst, " on ", len-1);
-               for (uint16_t i = 0; i < fpga_info_len; i++) {
-                       char c = (char)get_from_fpga_stream();
-                       if (i < sizeof(tempstr)) {
-                               tempstr[i] = c;
-                       }
-               }
-               strncat(dst, tempstr, len-1);
-       }
-       if(bitparse_find_section('d', &fpga_info_len)) {
-               strncat(dst, " at ", len-1);
-               for (uint16_t i = 0; i < fpga_info_len; i++) {
-                       char c = (char)get_from_fpga_stream();
-                       if (i < sizeof(tempstr)) {
-                               tempstr[i] = c;
-                       }
-               }
-               strncat(dst, tempstr, len-1);
-       }
-}

 
 //-----------------------------------------------------------------------------
 // Send a 16 bit command/data pair to the FPGA.
 
 //-----------------------------------------------------------------------------
 // Send a 16 bit command/data pair to the FPGA.


@@ -446,16 +456,30 @@ void FpgaSendCommand(uint16_t cmd, uint16_t v)
        while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0);              // wait for the transfer to complete
        AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v;         // send the data
 }
        while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0);              // wait for the transfer to complete
        AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v;         // send the data
 }

+

 //-----------------------------------------------------------------------------
 // Write the FPGA setup word (that determines what mode the logic is in, read
 // vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
 // avoid changing this function's occurence everywhere in the source code.
 //-----------------------------------------------------------------------------
 //-----------------------------------------------------------------------------
 // Write the FPGA setup word (that determines what mode the logic is in, read
 // vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
 // avoid changing this function's occurence everywhere in the source code.
 //-----------------------------------------------------------------------------

-void FpgaWriteConfWord(uint8_t v)
+void FpgaWriteConfWord(uint16_t v)

 {
        FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
 }
 
 {
        FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
 }
 

+//-----------------------------------------------------------------------------
+// enable/disable FPGA internal tracing
+//-----------------------------------------------------------------------------
+void FpgaEnableTracing(void)
+{
+       FpgaSendCommand(FPGA_CMD_TRACE_ENABLE, 1);
+}
+
+void FpgaDisableTracing(void)
+{
+       FpgaSendCommand(FPGA_CMD_TRACE_ENABLE, 0);
+}
+

 //-----------------------------------------------------------------------------
 // Set up the CMOS switches that mux the ADC: four switches, independently
 // closable, but should only close one at a time. Not an FPGA thing, but
 //-----------------------------------------------------------------------------
 // Set up the CMOS switches that mux the ADC: four switches, independently
 // closable, but should only close one at a time. Not an FPGA thing, but


@@ -482,3 +506,12 @@ void SetAdcMuxFor(uint32_t whichGpio)
 
        HIGH(whichGpio);
 }
 
        HIGH(whichGpio);
 }

+
+void Fpga_print_status(void) {
+       Dbprintf("Currently loaded FPGA image:");
+       Dbprintf("  %s", fpga_version_information[downloaded_bitstream-1]);
+}
+
+int FpgaGetCurrent() {
+       return downloaded_bitstream;
+}