Fix gcc10 compiler warnings

[proxmark3-svn] / fpga / fpga_lf.v

diff --git a/fpga/fpga_lf.v b/fpga/fpga_lf.v
index 1e20aa903a74d195c392672a1c47e69ff5d1f321..ac329653c0091316ac7109357dbca827e8d991b5 100644 (file)
--- a/fpga/fpga_lf.v
+++ b/fpga/fpga_lf.v
@@ -1,17 +1,28 @@
 //-----------------------------------------------------------------------------
 //-----------------------------------------------------------------------------

-// The FPGA is responsible for interfacing between the A/D, the coil drivers,
-// and the ARM. In the low-frequency modes it passes the data straight
-// through, so that the ARM gets raw A/D samples over the SSP. In the high-
-// frequency modes, the FPGA might perform some demodulation first, to
-// reduce the amount of data that we must send to the ARM.
-//
-// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
-// could be improved.
-//

 // Jonathan Westhues, March 2006
 // iZsh <izsh at fail0verflow.com>, June 2014
 //-----------------------------------------------------------------------------
 
 // Jonathan Westhues, March 2006
 // iZsh <izsh at fail0verflow.com>, June 2014
 //-----------------------------------------------------------------------------
 

+// Defining commands, modes and options. This must be aligned to the definitions in fpgaloader.h
+// Note: the definitions here are without shifts
+
+// Commands:
+`define FPGA_CMD_SET_CONFREG                        1
+`define FPGA_CMD_SET_DIVISOR                        2
+`define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD          3
+
+// Major modes:
+`define FPGA_MAJOR_MODE_LF_ADC                      0
+`define FPGA_MAJOR_MODE_LF_EDGE_DETECT              1
+`define FPGA_MAJOR_MODE_LF_PASSTHRU                 2
+
+// Options for LF_ADC
+`define FPGA_LF_ADC_READER_FIELD                    1
+
+// Options for LF_EDGE_DETECT
+`define FPGA_LF_EDGE_DETECT_READER_FIELD            1
+`define FPGA_LF_EDGE_DETECT_TOGGLE_MODE             2
+

 `include "lo_read.v"
 `include "lo_passthru.v"
 `include "lo_edge_detect.v"
 `include "lo_read.v"
 `include "lo_passthru.v"
 `include "lo_edge_detect.v"


@@ -38,33 +49,41 @@ module fpga_lf(
 
 reg [15:0] shift_reg;
 reg [7:0] divisor;
 
 reg [15:0] shift_reg;
 reg [7:0] divisor;

-reg [7:0] conf_word;
+reg [8:0] conf_word;
+reg [7:0] lf_ed_threshold;

 
 

-// We switch modes between transmitting to the 13.56 MHz tag and receiving
-// from it, which means that we must make sure that we can do so without
-// glitching, or else we will glitch the transmitted carrier.

 always @(posedge ncs)
 begin
 always @(posedge ncs)
 begin

-       case(shift_reg[15:12])
-               4'b0001: conf_word <= shift_reg[7:0];           // FPGA_CMD_SET_CONFREG
-               4'b0010: divisor <= shift_reg[7:0];             // FPGA_CMD_SET_DIVISOR
+       case (shift_reg[15:12])
+               `FPGA_CMD_SET_CONFREG:
+                       begin
+                               conf_word <= shift_reg[8:0];
+                               if (shift_reg[8:6] == `FPGA_MAJOR_MODE_LF_EDGE_DETECT)
+                               begin
+                                       lf_ed_threshold <= 127;                // default threshold
+                               end
+                       end
+               `FPGA_CMD_SET_DIVISOR:
+                       divisor <= shift_reg[7:0];
+               `FPGA_CMD_SET_EDGE_DETECT_THRESHOLD:
+                       lf_ed_threshold <= shift_reg[7:0];

        endcase
 end
 
 always @(posedge spck)
 begin
        endcase
 end
 
 always @(posedge spck)
 begin

-       if(~ncs)
+       if (~ncs)

        begin
                shift_reg[15:1] <= shift_reg[14:0];
                shift_reg[0] <= mosi;
        end
 end
 
        begin
                shift_reg[15:1] <= shift_reg[14:0];
                shift_reg[0] <= mosi;
        end
 end
 

-wire [2:0] major_mode;
-assign major_mode = conf_word[7:5];
+wire [2:0] major_mode = conf_word[8:6];

 
 // For the low-frequency configuration:
 wire lf_field = conf_word[0];
 
 // For the low-frequency configuration:
 wire lf_field = conf_word[0];

+wire lf_ed_toggle_mode = conf_word[1]; // for lo_edge_detect

 
 //-----------------------------------------------------------------------------
 // And then we instantiate the modules corresponding to each of the FPGA's
 
 //-----------------------------------------------------------------------------
 // And then we instantiate the modules corresponding to each of the FPGA's


@@ -80,7 +99,7 @@ lo_read lr(
        lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
        adc_d, lr_adc_clk,
        lr_ssp_frame, lr_ssp_din, lr_ssp_clk,
        lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
        adc_d, lr_adc_clk,
        lr_ssp_frame, lr_ssp_din, lr_ssp_clk,

-       lr_dbg
+       lr_dbg, lf_field

 );
 
 lo_passthru lp(
 );
 
 lo_passthru lp(


@@ -93,13 +112,14 @@ lo_passthru lp(
 );
 
 lo_edge_detect le(
 );
 
 lo_edge_detect le(

-       pck0, pck_cnt, pck_divclk,
+       pck0, pck_divclk,

        le_pwr_lo, le_pwr_hi, le_pwr_oe1, le_pwr_oe2, le_pwr_oe3, le_pwr_oe4,
        adc_d, le_adc_clk,
        le_ssp_frame, ssp_dout, le_ssp_clk,
        cross_lo,
        le_dbg,
        le_pwr_lo, le_pwr_hi, le_pwr_oe1, le_pwr_oe2, le_pwr_oe3, le_pwr_oe4,
        adc_d, le_adc_clk,
        le_ssp_frame, ssp_dout, le_ssp_clk,
        cross_lo,
        le_dbg,

-       lf_field
+       lf_field,
+       lf_ed_toggle_mode, lf_ed_threshold

 );
 
 // Major modes:
 );
 
 // Major modes:


@@ -107,17 +127,17 @@ lo_edge_detect le(
 //   001 --  LF edge detect (generic)
 //   010 --  LF passthrough
 
 //   001 --  LF edge detect (generic)
 //   010 --  LF passthrough
 

-mux8 mux_ssp_clk               (major_mode, ssp_clk,   lr_ssp_clk,   le_ssp_clk,         1'b0,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
-mux8 mux_ssp_din               (major_mode, ssp_din,   lr_ssp_din,         1'b0,         1'b0,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
-mux8 mux_ssp_frame             (major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame,       1'b0,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0); 
-mux8 mux_pwr_oe1               (major_mode, pwr_oe1,   lr_pwr_oe1,   le_pwr_oe1,   lp_pwr_oe1,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
-mux8 mux_pwr_oe2               (major_mode, pwr_oe2,   lr_pwr_oe2,   le_pwr_oe2,   lp_pwr_oe2,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0); 
-mux8 mux_pwr_oe3               (major_mode, pwr_oe3,   lr_pwr_oe3,   le_pwr_oe3,   lp_pwr_oe3,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
-mux8 mux_pwr_oe4               (major_mode, pwr_oe4,   lr_pwr_oe4,   le_pwr_oe4,   lp_pwr_oe4,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0); 
-mux8 mux_pwr_lo                        (major_mode, pwr_lo,    lr_pwr_lo,    le_pwr_lo,    lp_pwr_lo,    1'b0, 1'b0, 1'b0, 1'b0, 1'b0); 
-mux8 mux_pwr_hi                        (major_mode, pwr_hi,    lr_pwr_hi,    le_pwr_hi,    lp_pwr_hi,    1'b0, 1'b0, 1'b0, 1'b0, 1'b0); 
-mux8 mux_adc_clk               (major_mode, adc_clk,   lr_adc_clk,   le_adc_clk,   lp_adc_clk,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0); 
-mux8 mux_dbg                   (major_mode, dbg,       lr_dbg,       le_dbg,       lp_dbg,       1'b0, 1'b0, 1'b0, 1'b0, 1'b0); 
+mux8 mux_ssp_clk        (major_mode, ssp_clk,   lr_ssp_clk,   le_ssp_clk,   1'b0,         1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
+mux8 mux_ssp_din        (major_mode, ssp_din,   lr_ssp_din,   1'b0,         lp_ssp_din,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
+mux8 mux_ssp_frame      (major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame, 1'b0,         1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
+mux8 mux_pwr_oe1        (major_mode, pwr_oe1,   lr_pwr_oe1,   le_pwr_oe1,   lp_pwr_oe1,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
+mux8 mux_pwr_oe2        (major_mode, pwr_oe2,   lr_pwr_oe2,   le_pwr_oe2,   lp_pwr_oe2,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
+mux8 mux_pwr_oe3        (major_mode, pwr_oe3,   lr_pwr_oe3,   le_pwr_oe3,   lp_pwr_oe3,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
+mux8 mux_pwr_oe4        (major_mode, pwr_oe4,   lr_pwr_oe4,   le_pwr_oe4,   lp_pwr_oe4,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
+mux8 mux_pwr_lo         (major_mode, pwr_lo,    lr_pwr_lo,    le_pwr_lo,    lp_pwr_lo,    1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
+mux8 mux_pwr_hi         (major_mode, pwr_hi,    lr_pwr_hi,    le_pwr_hi,    lp_pwr_hi,    1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
+mux8 mux_adc_clk        (major_mode, adc_clk,   lr_adc_clk,   le_adc_clk,   lp_adc_clk,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
+mux8 mux_dbg            (major_mode, dbg,       lr_dbg,       le_dbg,       lp_dbg,       1'b0, 1'b0, 1'b0, 1'b0, 1'b0);

 
 // In all modes, let the ADC's outputs be enabled.
 assign adc_noe = 1'b0;
 
 // In all modes, let the ADC's outputs be enabled.
 assign adc_noe = 1'b0;