#include "lfsampling.h"
#include "protocols.h"
#include "usb_cdc.h" // for usb_poll_validate_length
+#include "fpgaloader.h"
/**
* Function to do a modulation and then get samples.
* and enlarge the gap ones.
* Q5 tags seems to have issues when these values changes.
*/
+ /*
+ // Original Timings for reference
+
#define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
#define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
#define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
#define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
#define READ_GAP 15*8
+*/
+
+// Structure to hold Timing values. In future will be simplier to add user changable timings.
+typedef struct {
+ uint16_t START_GAP;
+ uint16_t WRITE_GAP;
+ uint16_t WRITE_0;
+ uint16_t WRITE_1;
+ uint16_t WRITE_2;
+ uint16_t WRITE_3;
+ uint16_t READ_GAP;
+} T55xx_Timing;
+
+
+
+// Set Initial/Default Values. Note: *8 can occure when used. This should keep things simplier here.
+T55xx_Timing T55xx_Timing_FixedBit = { 31 * 8 , 20 * 8 , 18 * 8 , 50 * 8 , 0 , 0 , 15 * 8 };
+T55xx_Timing T55xx_Timing_LLR = { 31 * 8 , 20 * 8 , 18 * 8 , 50 * 8 , 0 , 0 , 15 * 8 };
+T55xx_Timing T55xx_Timing_Leading0 = { 31 * 8 , 20 * 8 , 18 * 8 , 40 * 8 , 0 , 0 , 15 * 8 };
+T55xx_Timing T55xx_Timing_1of4 = { 31 * 8 , 20 * 8 , 18 * 8 , 34 * 8 , 50 * 8 , 66 * 8 , 15 * 8 };
+
+
+// Some defines for readability
+#define T55xx_LongLeadingReference 4 // Value to tell Write Bit to send long reference
+#define T55xx_DLMode_Fixed 0 // Default Mode
+#define T55xx_DLMode_LLR 1 // Long Leading Reference
+#define T55xx_DLMode_Leading0 2 // Leading Zero
+#define T55xx_DLMode_1of4 3 // 1 of 4
void TurnReadLFOn(int delay) {
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
}
// Write one bit to card
-void T55xxWriteBit(int bit) {
- if (!bit)
- TurnReadLFOn(WRITE_0);
- else
- TurnReadLFOn(WRITE_1);
+void T55xxWriteBit(int bit, T55xx_Timing *Timings) {
+
+ // If bit = 4 Send Long Leading Reference which is 138 + WRITE_0
+
+ switch (bit){
+ case 0 : TurnReadLFOn(Timings->WRITE_0); break; // Send bit 0/00
+ case 1 : TurnReadLFOn(Timings->WRITE_1); break; // Send bit 1/01
+ case 2 : TurnReadLFOn(Timings->WRITE_2); break; // Send bits 10
+ case 3 : TurnReadLFOn(Timings->WRITE_3); break; // Send bits 11
+ case 4 : TurnReadLFOn(Timings->WRITE_0 + (136 * 8)); break; // Send Long Leading Reference
+ }
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
- WaitUS(WRITE_GAP);
+ WaitUS(Timings->WRITE_GAP);
+}
+
+
+// Function to abstract an Arbitrary length byte array to store bit pattern.
+// bit_array - Array to hold data/bit pattern
+// start_offset - bit location to start storing new bits.
+// data - upto 32 bits of data to store
+// num_bits - how many bits (low x bits of data) Max 32 bits at a time
+// max_len - how many bytes can the bit_array hold (ensure no buffer overflow)
+// returns "Next" bit offset / bits stored (for next store)
+int T55xx_SetBits (uint8_t *bit_array, int start_offset, uint32_t data , int num_bits, int max_len)
+{
+ int bit,byte_idx, bit_idx;
+ int offset;
+ int NextOffset = start_offset;
+
+ // Check if data will fit.
+ if ((start_offset + num_bits) <= (max_len*8)) {
+
+ // Loop through the data and store
+ for (offset = (num_bits-1); offset >= 0; offset--) {
+
+ bit = (data >> offset) & 1; // Get data bit value (0/1)
+ byte_idx = (NextOffset / 8); // Get Array Byte Index to Store
+ bit_idx = NextOffset - (byte_idx * 8); // Get Bit Index to set/clr
+
+ // If set (1) we OR, if clear (0) we AND with inverse
+ // Dbprintf ("Add Bit : %d at byte %d bit %d",bit,byte_idx,bit_idx);
+ if (bit == 1)
+ bit_array[byte_idx] |= (1 << bit_idx); // Set the bit to 1
+
+ else
+ bit_array[byte_idx] &= (0xff ^ (1 << bit_idx)); // Set the bit to 0 (clr)
+
+ NextOffset++;
+ }
+ }
+ else
+ Dbprintf ("Too Many Bits to fit into bit buffer");
+ return NextOffset;
}
// Send T5577 reset command then read stream (see if we can identify the start of the stream)
// Trigger T55x7 in mode.
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
- WaitUS(START_GAP);
+ WaitUS(T55xx_Timing_FixedBit.START_GAP);
// reset tag - op code 00
- T55xxWriteBit(0);
- T55xxWriteBit(0);
+ T55xxWriteBit(0,&T55xx_Timing_FixedBit);
+ T55xxWriteBit(0,&T55xx_Timing_FixedBit);
- TurnReadLFOn(READ_GAP);
+ TurnReadLFOn(T55xx_Timing_FixedBit.READ_GAP);
// Acquisition
DoPartialAcquisition(0, true, BigBuf_max_traceLen(), 0);
LED_A_OFF();
}
-// Write one card block in page 0, no lock
-void T55xxWriteBlockExt(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
- LED_A_ON();
- bool PwdMode = arg & 0x1;
- uint8_t Page = (arg & 0x2)>>1;
- bool testMode = arg & 0x4;
- uint32_t i = 0;
+// Send one downlink command to the card
+void T55xx_SendCMD (uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) { //, bool read_cmd) {//, struct T55xx_Timing *Timing) {
+
+ /*
+ arg bits
+ xxxxxxx1 0x01 PwdMode
+ xxxxxx1x 0x02 Page
+ xxxxx1xx 0x04 testMode
+ xxx11xxx 0x18 downlink mode
+ xx1xxxxx 0x20 reg_readmode
+ x1xxxxxx 0x40 called for a read, so no data packet
+
+ */
+ bool PwdMode = ((arg & 0x01) == 0x01);
+ uint8_t Page = (arg & 0x02) >> 1;
+ bool testMode = ((arg & 0x04) == 0x04);
+ uint8_t downlink_mode = (arg >> 3) & 0x03;;
+ bool reg_readmode = ((arg & 0x20) == 0x20);
+ bool read_cmd = ((arg & 0x40) == 0x40);
+
+ int i = 0;
+ uint8_t BitStream[10]; // Max Downlink Command size ~75 bits, so 10 bytes (80 bits)
+ uint8_t BitStreamLen;
+ int byte_idx, bit_idx;
+ T55xx_Timing *Timing;
+
+
+ // Assigning Downlink Timeing for write
+ switch (downlink_mode)
+ {
+ case T55xx_DLMode_Fixed : Timing = &T55xx_Timing_FixedBit; break;
+ case T55xx_DLMode_LLR : Timing = &T55xx_Timing_LLR; break;
+ case T55xx_DLMode_Leading0 : Timing = &T55xx_Timing_Leading0; break;
+ case T55xx_DLMode_1of4 : Timing = &T55xx_Timing_1of4; break;
+ default:
+ Timing = &T55xx_Timing_FixedBit;
+ }
+
+ // Build Bit Stream to send.
+ memset (BitStream,0x00,sizeof(BitStream));
+
+ BitStreamLen = 0;
+
+ // Add Leading 0 and 1 of 4 reference bit
+ if ((downlink_mode == T55xx_DLMode_Leading0) || (downlink_mode == T55xx_DLMode_1of4))
+ BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen, 0, 1,sizeof(BitStream));
+
+ // Add extra reference 0 for 1 of 4
+ if (downlink_mode == T55xx_DLMode_1of4)
+ BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen, 0, 1,sizeof(BitStream));
+
+ // Add Opcode
+ if (testMode) Dbprintf("TestMODE");
+ BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen,testMode ? 0 : 1 , 1,sizeof(BitStream));
+ BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen,testMode ? 1 : Page , 1,sizeof(BitStream));
+
+ if (PwdMode) {
+
+ // Leading 0 and 1 of 4 00 fixed bits if passsword used
+ if ((downlink_mode == T55xx_DLMode_Leading0) || (downlink_mode == T55xx_DLMode_1of4)) {
+ BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen, 0, 1,sizeof(BitStream));
+ BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen, 0, 1,sizeof(BitStream));
+ }
+ BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen, Pwd, 32,sizeof(BitStream));
+
+ }
+ // Add Lock bit
+ BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen, 0, 1,sizeof(BitStream));
+ // Add Data if a write command
+ if (!read_cmd) BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen, Data, 32,sizeof(BitStream));
+
+ // Add Address
+ if (!reg_readmode) BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen, Block, 3,sizeof(BitStream));
+
+
+
+ // Send Bits to T55xx
+
// Set up FPGA, 125kHz
LFSetupFPGAForADC(95, true);
StartTicks();
WaitMS(5);
// Trigger T55x7 in mode.
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
- WaitUS(START_GAP);
+ WaitUS(Timing->START_GAP);
- if (testMode) Dbprintf("TestMODE");
- // Std Opcode 10
- T55xxWriteBit(testMode ? 0 : 1);
- T55xxWriteBit(testMode ? 1 : Page); //Page 0
- if (PwdMode) {
- // Send Pwd
- for (i = 0x80000000; i != 0; i >>= 1)
- T55xxWriteBit(Pwd & i);
- }
- // Send Lock bit
- T55xxWriteBit(0);
+ // If long leading 0 send long reference pulse
+ if (downlink_mode == T55xx_DLMode_LLR)
+ T55xxWriteBit (T55xx_LongLeadingReference,Timing); // Send Long Leading Start Reference
- // Send Data
- for (i = 0x80000000; i != 0; i >>= 1)
- T55xxWriteBit(Data & i);
+ uint8_t SendBits;
+
+ if (downlink_mode == T55xx_DLMode_1of4) { // 1 of 4 need to send 2 bits at a time
+ for (i = 0; i < BitStreamLen; i+=2) {
+ byte_idx = i / 8;
+ bit_idx = i - (byte_idx * 8);
+ SendBits = ((BitStream[byte_idx] >> bit_idx) & 1) << 1;
+
+ byte_idx = (i+1) / 8;
+ bit_idx = (i+1) - (byte_idx * 8);
+ SendBits += (BitStream[byte_idx] >> bit_idx) & 1;
+
+ T55xxWriteBit (SendBits,Timing);
+ }
+ }
+ else {
+ for (i = 0; i < BitStreamLen; i++) {
+ byte_idx = i / 8;
+ bit_idx = i - (byte_idx * 8);
+ SendBits = (BitStream[byte_idx] >> bit_idx) & 1;
+ T55xxWriteBit (SendBits,Timing);
+ }
+ }
+
+}
- // Send Block number
- for (i = 0x04; i != 0; i >>= 1)
- T55xxWriteBit(Block & i);
+// Write one card block in page 0, no lock
+void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
+ /*
+ arg bits
+ xxxxxxx1 0x01 PwdMode
+ xxxxxx1x 0x02 Page
+ xxxxx1xx 0x04 testMode
+ xxx11xxx 0x18 downlink mode
+ xx1xxxxx 0x20 reg_readmode
+ x1xxxxxx 0x40 called for a read, so no data packet
+ */
+
+ bool testMode = ((arg & 0x04) == 0x04);
+ arg &= (0xff ^ 0x40); // Called for a write, so ensure it is clear/0
+
+ LED_A_ON ();
+ T55xx_SendCMD (Data, Block, Pwd, arg) ;//, false);
// Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
// so wait a little more)
//DoPartialAcquisition(20, true, 12000);
}
-
// turn field off
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
- LED_A_OFF();
-}
-
-// Write one card block in page 0, no lock
-void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
- T55xxWriteBlockExt(Data, Block, Pwd, arg);
+
cmd_send(CMD_ACK,0,0,0,0,0);
+
+ LED_A_OFF ();
}
// Read one card block in page [page]
-void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
+void T55xxReadBlock (uint16_t arg0, uint8_t Block, uint32_t Pwd) {//, struct T55xx_Timing *Timing) {
+
LED_A_ON();
- bool PwdMode = arg0 & 0x1;
- uint8_t Page = (arg0 & 0x2) >> 1;
- uint32_t i = 0;
- bool RegReadMode = (Block == 0xFF);//regular read mode
- //clear buffer now so it does not interfere with timing later
- BigBuf_Clear_ext(false);
+ /*
+ arg bits
+ xxxxxxx1 0x01 PwdMode
+ xxxxxx1x 0x02 Page
+ xxxxx1xx 0x04 testMode
+ xxx11xxx 0x18 downlink mode
+ xx1xxxxx 0x20 reg_readmode
+ x1xxxxxx 0x40 called for a read, so no data packet
+ */
+
+ // Set Read Flag to ensure SendCMD does not add "data" to the packet
+ arg0 |= 0x40;
+
+ if (Block == 0xff) arg0 |= 0x20;
+
//make sure block is at max 7
Block &= 0x7;
-
- // Set up FPGA, 125kHz to power up the tag
- LFSetupFPGAForADC(95, true);
- StartTicks();
- // make sure tag is fully powered up...
- WaitMS(5);
- // Trigger T55x7 Direct Access Mode with start gap
- FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
- WaitUS(START_GAP);
-
- // Opcode 1[page]
- T55xxWriteBit(1);
- T55xxWriteBit(Page); //Page 0
-
- if (PwdMode){
- // Send Pwd
- for (i = 0x80000000; i != 0; i >>= 1)
- T55xxWriteBit(Pwd & i);
- }
- // Send a zero bit separation
- T55xxWriteBit(0);
-
- // Send Block number (if direct access mode)
- if (!RegReadMode)
- for (i = 0x04; i != 0; i >>= 1)
- T55xxWriteBit(Block & i);
-
+ //clear buffer now so it does not interfere with timing later
+ BigBuf_Clear_ext(false);
+
+ T55xx_SendCMD (0, Block, Pwd, arg0); //, true);
+
+
// Turn field on to read the response
// 137*8 seems to get to the start of data pretty well...
// but we want to go past the start and let the repeating data settle in...
// Turn the field off
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
cmd_send(CMD_ACK,0,0,0,0,0);
+
LED_A_OFF();
}
// Trigger T55x7 Direct Access Mode
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
- WaitUS(START_GAP);
+ WaitUS(T55xx_Timing_FixedBit.START_GAP);
// Opcode 10
- T55xxWriteBit(1);
- T55xxWriteBit(0); //Page 0
+ T55xxWriteBit(1,&T55xx_Timing_FixedBit);
+ T55xxWriteBit(0,&T55xx_Timing_FixedBit); //Page 0
// Send Pwd
+
for (i = 0x80000000; i != 0; i >>= 1)
- T55xxWriteBit(Pwd & i);
+ T55xxWriteBit(Pwd & i,&T55xx_Timing_FixedBit);
// Turn and leave field on to let the begin repeating transmission
TurnReadLFOn(20*1000);
void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
// write last block first and config block last (if included)
for (uint8_t i = numblocks+startblock; i > startblock; i--) {
- T55xxWriteBlockExt(blockdata[i-1],i-1,0,0);
+ T55xxWriteBlock(blockdata[i-1],i-1,0,0);//,false); //,&T55xx_Timing_FixedBit);
+ // T55xx_SendCMD (blockdata[i-1],i-1,0,0);//,false); //,&T55xx_Timing_FixedBit);
}
}
-// Copy HID id to card and setup block 0 config
-void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
+// Copy a HID-like card (e.g. HID Proximity, Paradox) to a T55x7 compatible card
+void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT, uint8_t preamble) {
uint32_t data[] = {0,0,0,0,0,0,0};
uint8_t last_block = 0;
}
// Build the 6 data blocks for supplied 84bit ID
last_block = 6;
- // load preamble (1D) & long format identifier (9E manchester encoded)
- data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
+ // load preamble & long format identifier (9E manchester encoded)
+ data[1] = (preamble << 24) | 0x96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
// load raw id from hi2, hi, lo to data blocks (manchester encoded)
data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
data[3] = manchesterEncode2Bytes(hi >> 16);
data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
data[5] = manchesterEncode2Bytes(lo >> 16);
data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
- } else {
+ } else {
// Ensure no more than 44 bits supplied
if (hi>0xFFF) {
DbpString("Tags can only have 44 bits.");
// Build the 3 data blocks for supplied 44bit ID
last_block = 3;
// load preamble
- data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
+ data[1] = (preamble << 24) | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
data[2] = manchesterEncode2Bytes(lo >> 16);
data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
}
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
// Now set up the SSC to get the ADC samples that are now streaming at us.
- FpgaSetupSsc();
+ FpgaSetupSsc(FPGA_MAJOR_MODE_LF_ADC);
// start clock - 1.5ticks is 1us
StartTicks();
projects / proxmark3-svn / blobdiff