X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/1010aacca01ea823e5265babefa0d325863a2ba3..9b989c45b942356410416b10e96bc4ca624e4563:/armsrc/lfops.c diff --git a/armsrc/lfops.c b/armsrc/lfops.c index bf743c24..1a7c3224 100644 --- a/armsrc/lfops.c +++ b/armsrc/lfops.c @@ -17,6 +17,9 @@ #include "crapto1.h" #include "mifareutil.h" +#define SHORT_COIL() LOW(GPIO_SSC_DOUT) +#define OPEN_COIL() HIGH(GPIO_SSC_DOUT) + void LFSetupFPGAForADC(int divisor, bool lf_field) { FpgaDownloadAndGo(FPGA_BITSTREAM_LF); @@ -56,10 +59,9 @@ void DoAcquisition125k_internal(int trigger_threshold, bool silent) { uint8_t *dest = mifare_get_bigbufptr(); int n = 24000; - int i; - + int i = 0; memset(dest, 0x00, n); - i = 0; + for(;;) { if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { AT91C_BASE_SSC->SSC_THR = 0x43; @@ -289,17 +291,17 @@ void WriteTIbyte(uint8_t b) { if (b&(1<PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK; - - AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; - AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK; - -#define SHORT_COIL() LOW(GPIO_SSC_DOUT) -#define OPEN_COIL() HIGH(GPIO_SSC_DOUT) - - i = 0; - for(;;) { - while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) { - if(BUTTON_PRESS()) { - DbpString("Stopped"); - return; - } - WDT_HIT(); + FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz + //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT); + FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); + + // Connect the A/D to the peak-detected low-frequency path. + //SetAdcMuxFor(GPIO_MUXSEL_LOPKD); + + // Configure output and enable pin that is connected to the FPGA (for modulating) + AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK; + AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; // (PIO_PER) PIO Enable Register , + AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; // (PIO_OER) Output Enable Register + AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK; // (PIO_ODR) Output Disable Register + + // Give it a bit of time for the resonant antenna to settle. + SpinDelay(150); + + while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high + while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK); // wait for ssp_clk to go low + + while(!BUTTON_PRESS()) { + WDT_HIT(); + + // PIO_PDSR = Pin Data Status Register + // GPIO_SSC_CLK = SSC Transmit Clock + while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) { // wait for ssp_clk to go high + if(BUTTON_PRESS()) { + DbpString("Stopped at 0"); + FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off + return; + } + WDT_HIT(); } - if (ledcontrol) - LED_D_ON(); - - if(tab[i]) - OPEN_COIL(); - else - SHORT_COIL(); - - if (ledcontrol) - LED_D_OFF(); - - while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) { - if(BUTTON_PRESS()) { - DbpString("Stopped"); + // PIO_CODR = Clear Output Data Register + // PIO_SODR = Set Output Data Register + //#define LOW(x) AT91C_BASE_PIOA->PIO_CODR = (x) + //#define HIGH(x) AT91C_BASE_PIOA->PIO_SODR = (x) + + if ( buf[i] > 0 ){ + HIGH(GPIO_SSC_DOUT); + //FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz + //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); + } else { + LOW(GPIO_SSC_DOUT); + //FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); + } + + while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) { // wait for ssp_clk to go low + if(BUTTON_PRESS()) { + DbpString("Stopped at 1"); + FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off return; } WDT_HIT(); - } - - i++; + } + + //SpinDelayUs(512); + + ++i; if(i == period) { i = 0; if (gap) { - SHORT_COIL(); - SpinDelayUs(gap); - } + // turn of modulation + LOW(GPIO_SSC_DOUT); + // wait + SpinDelay(gap); + } } } + DbpString("Stopped"); + FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); + return; } #define DEBUG_FRAME_CONTENTS 1 @@ -605,6 +631,7 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol) if (ledcontrol) LED_A_ON(); + SimulateTagLowFrequency(n, 0, ledcontrol); if (ledcontrol) @@ -789,8 +816,6 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol) LFSetupFPGAForADC(0, true); while(!BUTTON_PRESS()) { - - WDT_HIT(); if (ledcontrol) LED_A_ON();