X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/2bfed17db25367442c6ad57a76a3c998ec84889c..c68f5fc7ec56cb0c7fc048a45f51684ab6ea096c:/bootrom/ldscript-flash

diff --git a/bootrom/ldscript-flash b/bootrom/ldscript-flash
index 50218d68..f1bab149 100644
--- a/bootrom/ldscript-flash
+++ b/bootrom/ldscript-flash
@@ -1,32 +1,63 @@
-INCLUDE ../common/ldscript.common
-
-ENTRY(flashstart)
-SECTIONS
-{
-    . = 0;
-    
-    bootphase1 : {
-    	*(.startup) 
-    	*(.bootphase1)
-    } >bootphase1
-    
-    bootphase2 : {
-    	__bootphase2_start__ = .;
-    	*(.startphase2)
-    	*(.text)
-    	*(.glue_7)
-    	*(.glue_7t)
-    	*(.rodata)
-        *(.data)
-    	. = ALIGN( 32 / 8 );
-    	__bootphase2_end__ = .;
-    } >ram AT>bootphase2
-    
-    .bss : {
-    	__bss_start__ = .; 
-    	*(.bss)
-    } >ram
-    
-    . = ALIGN( 32 / 8 );
-    __bss_end__ = .;
-}
+/*
+-----------------------------------------------------------------------------
+ This code is licensed to you under the terms of the GNU GPL, version 2 or,
+ at your option, any later version. See the LICENSE.txt file for the text of
+ the license.
+-----------------------------------------------------------------------------
+ Bootrom linker script
+-----------------------------------------------------------------------------
+*/
+
+INCLUDE ../common/ldscript.common
+
+PHDRS
+{
+	phase1 PT_LOAD;
+	phase2 PT_LOAD;
+	bss PT_LOAD;
+}
+
+ENTRY(flashstart)
+SECTIONS
+{
+	.bootphase1 : {
+		*(.startup)
+
+		. = ALIGN(4);
+		_version_information_start = .;
+		KEEP(*(.version_information));
+
+		. = LENGTH(bootphase1) - 0x4;
+		LONG(_version_information_start);
+	} >bootphase1 :phase1
+
+	.bootphase2 : {
+		*(.startphase2)
+		*(.text)
+		*(.text.*)
+		*(.eh_frame)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.rodata)
+		*(.rodata.*)
+		*(.data)
+		*(.data.*)
+		. = ALIGN(4);
+	} >ram AT>bootphase2 :phase2
+
+	__bootphase2_src_start__ = LOADADDR(.bootphase2);
+	__bootphase2_start__ = ADDR(.bootphase2);
+	__bootphase2_end__ = __bootphase2_start__ + SIZEOF(.bootphase2);
+
+	.bss : {
+		__bss_start__ = .;
+		*(.bss)
+		*(.bss.*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} >ram AT>ram :bss
+
+	.commonarea (NOLOAD) : {
+		*(.commonarea)
+	} >commonarea
+}