X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/36f84d474844a67f389239c0ec361f0dfe88983a..da8279796e4438b19442fad89c31b4955751877e:/fpga/hi_read_rx_xcorr.v

diff --git a/fpga/hi_read_rx_xcorr.v b/fpga/hi_read_rx_xcorr.v
index f816199e..f3e4fecd 100644
--- a/fpga/hi_read_rx_xcorr.v
+++ b/fpga/hi_read_rx_xcorr.v
@@ -15,9 +15,9 @@ module hi_read_rx_xcorr(
     input pck0, ck_1356meg, ck_1356megb;
     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
     input [7:0] adc_d;
-    output adc_clk;
+    output adc_clk, ssp_frame, ssp_din;
     input ssp_dout;
-    output ssp_frame, ssp_din, ssp_clk;
+    output ssp_clk;
     input cross_hi, cross_lo;
     output dbg;
     input xcorr_is_848, snoop;
@@ -88,21 +88,21 @@ begin
     // These are the correlators: we correlate against in-phase and quadrature
     // versions of our reference signal, and keep the (signed) result to
     // send out later over the SSP.
-    if(corr_i_cnt == 7'd0)
+    if(corr_i_cnt == 6'd0)
     begin
         if(snoop)
-        begin
-			// Send only 7 most significant bits of tag signal (signed), LSB is reader signal:
-            corr_i_out <= {corr_i_accum[13:7], after_hysteresis_prev_prev};
-            corr_q_out <= {corr_q_accum[13:7], after_hysteresis_prev};
-			after_hysteresis_prev_prev <= after_hysteresis;
-        end
+			begin
+				// Send only 7 most significant bits of tag signal (signed), LSB is reader signal:
+				corr_i_out <= {corr_i_accum[13:7], after_hysteresis_prev_prev};
+				corr_q_out <= {corr_q_accum[13:7], after_hysteresis_prev};
+				after_hysteresis_prev_prev <= after_hysteresis;
+			end
         else
-        begin
-            // 8 most significant bits of tag signal
-            corr_i_out <= corr_i_accum[13:6];
-            corr_q_out <= corr_q_accum[13:6];
-        end
+			begin
+				// 8 most significant bits of tag signal
+				corr_i_out <= corr_i_accum[13:6];
+				corr_q_out <= corr_q_accum[13:6];
+			end
 
         corr_i_accum <= adc_d;
         corr_q_accum <= adc_d;
@@ -123,7 +123,7 @@ begin
 
     // The logic in hi_simulate.v reports 4 samples per bit. We report two
     // (I, Q) pairs per bit, so we should do 2 samples per pair.
-    if(corr_i_cnt == 6'd31)
+    if(corr_i_cnt == 6'd32)
         after_hysteresis_prev <= after_hysteresis;
 
     // Then the result from last time is serialized and send out to the ARM.