X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/4058a2d7df35e5a4f59f80ae1b4aa7d7598056dc..050aa18b13084b0d57ffcee352bf7a30b828b8f5:/armsrc/util.c

diff --git a/armsrc/util.c b/armsrc/util.c
index e25c6e0b..a1b0f151 100644
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -81,11 +81,6 @@ void lsl (uint8_t *data, size_t len) {
     data[len - 1] <<= 1;
 }
 
-int32_t le24toh (uint8_t data[3])
-{
-    return (data[2] << 16) | (data[1] << 8) | data[0];
-}
-
 void LEDsoff()
 {
 	LED_A_OFF();
@@ -448,31 +443,52 @@ uint32_t RAMFUNC GetCountSspClk(){
 
 
 //  -------------------------------------------------------------------------
-//  Timer for bitbanging,  or LF stuff when you need a very precis timer
+//  Timer for bitbanging, or LF stuff when you need a very precis timer
 //  1us = 1.5ticks
 //  -------------------------------------------------------------------------
 void StartTicks(void){
-	//initialization of the timer
-	// tc1 is higher 0xFFFF0000
-	// tc0 is lower 0x0000FFFF
+	// initialization of the timer
 	AT91C_BASE_PMC->PMC_PCER |= (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1);
 	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
+
+	// disable TC0 and TC1 for re-configuration
 	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
+	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
+
+	// first configure TC1 (higher, 0xFFFF0000) 16 bit counter
+	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // just connect to TIOA0 from TC0
+	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // re-enable timer and wait for TC0
+
+	// second configure TC0 (lower, 0x0000FFFF) 16 bit counter
 	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32 
-								AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
-								AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
-	AT91C_BASE_TC0->TC_RA = 1;
-	AT91C_BASE_TC0->TC_RC = 0; 
+	                         AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO |
+	                         AT91C_TC_ACPA_CLEAR | // RA comperator clears TIOA (carry bit)
+	                         AT91C_TC_ACPC_SET |   // RC comperator sets TIOA (carry bit)
+	                         AT91C_TC_ASWTRG_SET;  // SWTriger sets TIOA (carry bit)
+	AT91C_BASE_TC0->TC_RC  = 0; // set TIOA (carry bit) on overflow, return to zero
+	AT91C_BASE_TC0->TC_RA  = 1; // clear carry bit on next clock cycle
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // reset and re-enable timer
+
+	// synchronized startup procedure
+	while (AT91C_BASE_TC0->TC_CV > 0); // wait until TC0 returned to zero
+	while (AT91C_BASE_TC0->TC_CV < 2); // and has started (TC_CV > TC_RA, now TC1 is cleared)
+
+	// return to zero
+	AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
+	while (AT91C_BASE_TC0->TC_CV > 0);
+}
 
-	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;	// timer disable  
-	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from TC0
-	
-	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
-	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
-	AT91C_BASE_TCB->TCB_BCR = 1;
-	
-	// wait until timer becomes zero.
-	while (AT91C_BASE_TC1->TC_CV > 0);
+
+uint32_t GetTicks(void) {
+	uint32_t hi, lo;
+
+	do {
+		hi = AT91C_BASE_TC1->TC_CV;
+		lo = AT91C_BASE_TC0->TC_CV;
+	} while(hi != AT91C_BASE_TC1->TC_CV);
+
+	return (hi << 16) | lo;
 }
 
 
@@ -480,30 +496,28 @@ void StartTicks(void){
 // if called with a high number, this will trigger the WDT...
 void WaitTicks(uint32_t ticks){
 	if ( ticks == 0 ) return;
-	ticks += GET_TICKS;	
-	while (GET_TICKS < ticks);
+	ticks += GetTicks();
+	while (GetTicks() < ticks);
 }
 
 
 // Wait / Spindelay in us (microseconds) 
 // 1us = 1.5ticks.
 void WaitUS(uint16_t us){
-	if ( us == 0 ) return;
-	WaitTicks(  (uint32_t)(us * 1.5) );
+	WaitTicks( (uint32_t)us * 3 / 2 ) ;
 }
 
 
 void WaitMS(uint16_t ms){
-	if (ms == 0) return;
-	WaitTicks( (uint32_t)(ms * 1500) );
+	WaitTicks( (uint32_t)ms * 1500 );
 }
 
 
 // Starts Clock and waits until its reset
 void ResetTicks(void){
-	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
-	while (AT91C_BASE_TC1->TC_CV > 0);
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+	while (AT91C_BASE_TC0->TC_CV > 0);
 }