X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/4c8db262c093fff0334a048526a69112f939edac..15cdabd474e7c90bc86fc8c1f2a1ca854ea9f6da:/armsrc/legicrf.c diff --git a/armsrc/legicrf.c b/armsrc/legicrf.c index 5b0bf37a..313ac3c9 100644 --- a/armsrc/legicrf.c +++ b/armsrc/legicrf.c @@ -1,16 +1,19 @@ -/* - * LEGIC RF simulation code - * - * (c) 2009 Henryk Plötz - */ - -#include - +//----------------------------------------------------------------------------- +// (c) 2009 Henryk Plötz +// +// This code is licensed to you under the terms of the GNU GPL, version 2 or, +// at your option, any later version. See the LICENSE.txt file for the text of +// the license. +//----------------------------------------------------------------------------- +// LEGIC RF simulation code +//----------------------------------------------------------------------------- + +#include "proxmark3.h" #include "apps.h" -#include "legicrf.h" -#include "unistd.h" -#include "stdint.h" +#include "util.h" +#include "string.h" +#include "legicrf.h" #include "legic_prng.h" #include "crc.h" @@ -31,7 +34,7 @@ static void setup_timer(void) AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1); timer = AT91C_BASE_TC1; timer->TC_CCR = AT91C_TC_CLKDIS; - timer->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK3; + timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK; timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; /* At TIMER_CLOCK3 (MCK/32) */ @@ -54,7 +57,7 @@ static void frame_send_rwd(uint32_t data, int bits) /* Start clock */ timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; while(timer->TC_CV > 1) ; /* Wait till the clock has reset */ - + int i; for(i=0; iTC_CV; @@ -67,17 +70,17 @@ static void frame_send_rwd(uint32_t data, int bits) } else { bit_end = starttime + RWD_TIME_0; } - + /* RWD_TIME_PAUSE time off, then some time on, so that the complete bit time is * RWD_TIME_x, where x is the bit to be transmitted */ AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT; while(timer->TC_CV < pause_end) ; AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT; legic_prng_forward(1); /* bit duration is longest. use this time to forward the lfsr */ - + while(timer->TC_CV < bit_end) ; } - + { /* One final pause to mark the end of the frame */ int pause_end = timer->TC_CV + RWD_TIME_PAUSE; @@ -85,7 +88,7 @@ static void frame_send_rwd(uint32_t data, int bits) while(timer->TC_CV < pause_end) ; AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT; } - + /* Reset the timer, to measure time until the start of the tag frame */ timer->TC_CCR = AT91C_TC_SWTRG; while(timer->TC_CV > 1) ; /* Wait till the clock has reset */ @@ -93,12 +96,12 @@ static void frame_send_rwd(uint32_t data, int bits) /* Receive a frame from the card in reader emulation mode, the FPGA and * timer must have been set up by LegicRfReader and frame_send_rwd. - * + * * The LEGIC RF protocol from card to reader does not include explicit * frame start/stop information or length information. The reader must * know beforehand how many bits it wants to receive. (Notably: a card * sending a stream of 0-bits is indistinguishable from no card present.) - * + * * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but * I'm not smart enough to use it. Instead I have patched hi_read_tx to output * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look @@ -107,10 +110,10 @@ static void frame_send_rwd(uint32_t data, int bits) * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the * timer that's still running from frame_send_rwd in order to get a synchronization * with the frame that we just sent. - * - * FIXME: Because we're relying on the hysteresis to just do the right thing + * + * FIXME: Because we're relying on the hysteresis to just do the right thing * the range is severely reduced (and you'll probably also need a good antenna). - * So this should be fixed some time in the future for a proper receiver. + * So this should be fixed some time in the future for a proper receiver. */ static void frame_receive_rwd(struct legic_frame * const f, int bits, int crypt) { @@ -118,8 +121,8 @@ static void frame_receive_rwd(struct legic_frame * const f, int bits, int crypt) uint32_t data=0; int i, old_level=0, edges=0; int next_bit_at = TAG_TIME_WAIT; - - + + if(bits > 16) bits = 16; @@ -141,7 +144,7 @@ static void frame_receive_rwd(struct legic_frame * const f, int bits, int crypt) while(timer->TC_CV < next_bit_at) ; next_bit_at += TAG_TIME_BIT; - + for(i=0; i 20 && edges < 60) { /* expected are 42 edges */ data ^= the_bit; } the_bit <<= 1; } - + f->data = data; f->bits = bits; - + /* Reset the timer, to synchronize the next frame */ timer->TC_CCR = AT91C_TC_SWTRG; while(timer->TC_CV > 1) ; /* Wait till the clock has reset */ @@ -176,15 +179,15 @@ static void frame_clean(struct legic_frame * const f) static uint32_t perform_setup_phase_rwd(int iv) { - + /* Switch on carrier and let the tag charge for 1ms */ AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT; SpinDelay(1); - + legic_prng_init(0); /* no keystream yet */ frame_send_rwd(iv, 7); legic_prng_init(iv); - + frame_clean(¤t_frame); frame_receive_rwd(¤t_frame, 6, 1); legic_prng_forward(1); /* we wait anyways */ @@ -198,14 +201,14 @@ static void LegicCommonInit(void) { SetAdcMuxFor(GPIO_MUXSEL_HIPKD); FpgaSetupSsc(); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX); - + /* Bitbang the transmitter */ AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; - + setup_timer(); - + crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0); } @@ -214,7 +217,7 @@ static void switch_off_tag_rwd(void) /* Switch off carrier, make sure tag is reset */ AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT; SpinDelay(10); - + WDT_HIT(); } /* calculate crc for a legic command */ @@ -257,11 +260,11 @@ int legic_read_byte(int byte_index, int cmd_sz) { void LegicRfReader(int offset, int bytes) { int byte_index=0, cmd_sz=0, card_sz=0; - + LegicCommonInit(); memset(BigBuf, 0, 1024); - + DbpString("setting up legic card"); uint32_t tag_type = perform_setup_phase_rwd(0x55); switch(tag_type) {