X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/660d641a03456e99ea83c68dbd3d03bae2b64573..d2d0af8ca61484f1460ea302e6bcc2e1cac71297:/armsrc/lfops.c

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index 8d4e2dc9..6b131c26 100644
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -15,30 +15,40 @@
 #include "crc16.h"
 #include "string.h"
 
-void AcquireRawAdcSamples125k(int at134khz)
+void LFSetupFPGAForADC(int divisor, bool lf_field)
 {
-	if (at134khz)
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+	if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
 		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-	else
+	else if (divisor == 0)
 		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+	else
+		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
 
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
 
 	// Connect the A/D to the peak-detected low-frequency path.
 	SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
-
 	// Give it a bit of time for the resonant antenna to settle.
 	SpinDelay(50);
-
 	// Now set up the SSC to get the ADC samples that are now streaming at us.
 	FpgaSetupSsc();
+}
 
-	// Now call the acquisition routine
-	DoAcquisition125k();
+void AcquireRawAdcSamples125k(int divisor)
+{
+	LFSetupFPGAForADC(divisor, true);
+	DoAcquisition125k(-1);
+}
+
+void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
+{
+	LFSetupFPGAForADC(divisor, false);
+	DoAcquisition125k(trigger_threshold);
 }
 
 // split into two routines so we can avoid timing issues after sending commands //
-void DoAcquisition125k(void)
+void DoAcquisition125k(int trigger_threshold)
 {
 	uint8_t *dest = (uint8_t *)BigBuf;
 	int n = sizeof(BigBuf);
@@ -53,9 +63,12 @@ void DoAcquisition125k(void)
 		}
 		if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
 			dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
-			i++;
 			LED_D_OFF();
-			if (i >= n) break;
+			if (trigger_threshold != -1 && dest[i] < trigger_threshold)
+				continue;
+			else
+				trigger_threshold = -1;
+			if (++i >= n) break;
 		}
 	}
 	Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
@@ -67,6 +80,7 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
 	int at134khz;
 
 	/* Make sure the tag is reset */
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 	SpinDelay(2500);
 
@@ -81,7 +95,7 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
 	else
 		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
 	// Give it a bit of time for the resonant antenna to settle.
 	SpinDelay(50);
@@ -101,7 +115,7 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
 		else
 			FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 
-		FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+		FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 		LED_D_ON();
 		if(*(command++) == '0')
 			SpinDelayUs(period_0);
@@ -116,10 +130,10 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
 	else
 		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
 	// now do the read
-	DoAcquisition125k();
+	DoAcquisition125k(-1);
 }
 
 /* blank r/w tag data stream
@@ -156,6 +170,7 @@ void ReadTItag(void)
 	uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
 
 	// TI tags charge at 134.2Khz
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
 
 	// Place FPGA in passthrough mode, in this mode the CROSS_LO line
@@ -363,6 +378,7 @@ void AcquireTiType(void)
 // if not provided a valid crc will be computed from the data and written.
 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
 {
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);	
 	if(crc == 0) {
 	 	crc = update_crc16(crc, (idlo)&0xff);
 		crc = update_crc16(crc, (idlo>>8)&0xff);
@@ -434,6 +450,7 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 	int i;
 	uint8_t *tab = (uint8_t *)BigBuf;
     
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
     
 	AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
@@ -600,8 +617,9 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 	int m=0, n=0, i=0, idx=0, found=0, lastval=0;
   uint32_t hi2=0, hi=0, lo=0;
 
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
 	// Connect the A/D to the peak-detected low-frequency path.
 	SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
@@ -805,6 +823,265 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 	}
 }
 
+void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
+{
+	uint8_t *dest = (uint8_t *)BigBuf;
+	int m=0, n=0, i=0, idx=0, lastval=0;
+	int found=0;
+	uint32_t code=0, code2=0;
+	//uint32_t hi2=0, hi=0, lo=0;
+
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
+
+	// Connect the A/D to the peak-detected low-frequency path.
+	SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+
+	// Give it a bit of time for the resonant antenna to settle.
+	SpinDelay(50);
+
+	// Now set up the SSC to get the ADC samples that are now streaming at us.
+	FpgaSetupSsc();
+
+	for(;;) {
+		WDT_HIT();
+		if (ledcontrol)
+			LED_A_ON();
+		if(BUTTON_PRESS()) {
+			DbpString("Stopped");
+			if (ledcontrol)
+				LED_A_OFF();
+			return;
+		}
+
+		i = 0;
+		m = sizeof(BigBuf);
+		memset(dest,128,m);
+		for(;;) {
+			if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+				AT91C_BASE_SSC->SSC_THR = 0x43;
+				if (ledcontrol)
+					LED_D_ON();
+			}
+			if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
+				dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
+				// we don't care about actual value, only if it's more or less than a
+				// threshold essentially we capture zero crossings for later analysis
+				if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
+				i++;
+				if (ledcontrol)
+					LED_D_OFF();
+				if(i >= m) {
+					break;
+				}
+			}
+		}
+
+		// FSK demodulator
+
+		// sync to first lo-hi transition
+		for( idx=1; idx<m; idx++) {
+			if (dest[idx-1]<dest[idx])
+				lastval=idx;
+				break;
+		}
+		WDT_HIT();
+
+		// count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
+		// or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
+		// between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
+		for( i=0; idx<m; idx++) {
+			if (dest[idx-1]<dest[idx]) {
+				dest[i]=idx-lastval;
+				if (dest[i] <= 8) {
+						dest[i]=1;
+				} else {
+						dest[i]=0;
+				}
+
+				lastval=idx;
+				i++;
+			}
+		}
+		m=i;
+		WDT_HIT();
+
+		// we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
+		lastval=dest[0];
+		idx=0;
+		i=0;
+		n=0;
+		for( idx=0; idx<m; idx++) {
+			if (dest[idx]==lastval) {
+				n++;
+			} else {
+				// a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,
+				// an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets
+				// swallowed up by rounding
+				// expected results are 1 or 2 bits, any more and it's an invalid manchester encoding
+				// special start of frame markers use invalid manchester states (no transitions) by using sequences
+				// like 111000
+				if (dest[idx-1]) {
+					n=(n+1)/7;			// fc/8 in sets of 7
+				} else {
+					n=(n+1)/6;			// fc/10 in sets of 6
+				}
+				switch (n) {			// stuff appropriate bits in buffer
+					case 0:
+					case 1:	// one bit
+						dest[i++]=dest[idx-1]^1;
+						//Dbprintf("%d",dest[idx-1]);
+						break;
+					case 2: // two bits
+						dest[i++]=dest[idx-1]^1;
+						dest[i++]=dest[idx-1]^1;
+						//Dbprintf("%d",dest[idx-1]);
+						//Dbprintf("%d",dest[idx-1]);
+						break;
+					case 3: // 3 bit start of frame markers
+						for(int j=0; j<3; j++){
+						  dest[i++]=dest[idx-1]^1;
+						//  Dbprintf("%d",dest[idx-1]);
+						}
+						break;
+					case 4:
+						for(int j=0; j<4; j++){
+						  dest[i++]=dest[idx-1]^1;
+						//  Dbprintf("%d",dest[idx-1]);
+						}
+						break;
+					case 5:
+						for(int j=0; j<5; j++){
+						  dest[i++]=dest[idx-1]^1;
+						//  Dbprintf("%d",dest[idx-1]);
+						}
+						break;
+					case 6:
+						for(int j=0; j<6; j++){
+						  dest[i++]=dest[idx-1]^1;
+						//  Dbprintf("%d",dest[idx-1]);
+						}
+						break;
+					case 7:
+						for(int j=0; j<7; j++){
+						  dest[i++]=dest[idx-1]^1;
+						//  Dbprintf("%d",dest[idx-1]);
+						}
+						break;
+					case 8:
+						for(int j=0; j<8; j++){
+						  dest[i++]=dest[idx-1]^1;
+						//  Dbprintf("%d",dest[idx-1]);
+						}
+						break;
+					case 9:
+						for(int j=0; j<9; j++){
+						  dest[i++]=dest[idx-1]^1;
+						//  Dbprintf("%d",dest[idx-1]);
+						}
+						break;
+					case 10:
+						for(int j=0; j<10; j++){
+						  dest[i++]=dest[idx-1]^1;
+						//  Dbprintf("%d",dest[idx-1]);
+						}
+						break;
+					case 11:
+						for(int j=0; j<11; j++){
+						  dest[i++]=dest[idx-1]^1;
+						//  Dbprintf("%d",dest[idx-1]);
+						}
+						break;
+					case 12:
+						for(int j=0; j<12; j++){
+						  dest[i++]=dest[idx-1]^1;
+						 // Dbprintf("%d",dest[idx-1]);
+						}
+						break;
+					default:	// this shouldn't happen, don't stuff any bits
+						//Dbprintf("%d",dest[idx-1]);
+						break;
+				}
+				n=0;
+				lastval=dest[idx];
+			}
+		}//end for
+		/*for(int j=0; j<64;j+=8){
+		  Dbprintf("%d%d%d%d%d%d%d%d",dest[j],dest[j+1],dest[j+2],dest[j+3],dest[j+4],dest[j+5],dest[j+6],dest[j+7]);
+		}
+		Dbprintf("\n");*/
+		m=i;
+		WDT_HIT();
+		
+        for( idx=0; idx<m-9; idx++) {
+	  if ( !(dest[idx]) && !(dest[idx+1]) && !(dest[idx+2]) && !(dest[idx+3]) && !(dest[idx+4]) && !(dest[idx+5]) && !(dest[idx+6]) && !(dest[idx+7]) && !(dest[idx+8])&& (dest[idx+9])){
+		found=1;
+		//idx+=9;
+		if (found) {
+		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx],   dest[idx+1],   dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7]);
+		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+8], dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15]);			  
+		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+16],dest[idx+17],dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23]);
+		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+24],dest[idx+25],dest[idx+26],dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31]);
+		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35],dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39]);
+		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44],dest[idx+45],dest[idx+46],dest[idx+47]);
+		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53],dest[idx+54],dest[idx+55]);
+		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
+		
+		    short version='\x00';
+		    char unknown='\x00';
+		    uint16_t number=0;
+		    for(int j=14;j<18;j++){
+		       //Dbprintf("%d",dest[idx+j]);
+		       version <<=1;
+		       if (dest[idx+j]) version |= 1;
+		    }
+		    for(int j=19;j<27;j++){
+		       //Dbprintf("%d",dest[idx+j]);
+		       unknown <<=1;
+		       if (dest[idx+j]) unknown |= 1;
+		    }
+		    for(int j=36;j<45;j++){
+		       //Dbprintf("%d",dest[idx+j]);
+		       number <<=1;
+		       if (dest[idx+j]) number |= 1;
+		    }
+		    for(int j=46;j<53;j++){
+		       //Dbprintf("%d",dest[idx+j]);
+		       number <<=1;
+		       if (dest[idx+j]) number |= 1;
+		    }
+		    for(int j=0; j<32; j++){
+			code <<=1;
+			if(dest[idx+j]) code |= 1;
+		    }
+		    for(int j=32; j<64; j++){
+			code2 <<=1;
+			if(dest[idx+j]) code2 |= 1;
+		    }
+		    
+		    Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,unknown,number,code,code2);
+		    if (ledcontrol)
+			LED_D_OFF();
+		}
+		// if we're only looking for one tag 
+		if (findone){
+			//*high = hi;
+			//*low = lo;
+			LED_A_OFF();
+			return;
+		}
+      
+		//hi=0;
+		//lo=0;
+		found=0;
+	  }
+		
+	}
+	}
+	WDT_HIT();
+}
+
 /*------------------------------
  * T5555/T5557/T5567 routines
  *------------------------------
@@ -872,8 +1149,9 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 // Write one bit to card
 void T55xxWriteBit(int bit)
 {
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 	if (bit == 0)
 		SpinDelayUs(WRITE_0);
 	else
@@ -887,8 +1165,9 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
 {
 	unsigned int i;
 
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
 	// Give it a bit of time for the resonant antenna to settle.
 	// And for the tag to fully power up
@@ -920,7 +1199,7 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
 	// Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
 	// so wait a little more)
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 	SpinDelay(20);
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 }
@@ -931,6 +1210,7 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 	uint8_t *dest = (uint8_t *)BigBuf;
 	int m=0, i=0;
   
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	m = sizeof(BigBuf);
   // Clear destination buffer before sending the command
 	memset(dest, 128, m);
@@ -941,7 +1221,7 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
   
 	LED_D_ON();
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
   
 	// Give it a bit of time for the resonant antenna to settle.
 	// And for the tag to fully power up
@@ -967,7 +1247,7 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
   
   // Turn field on to read the response
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
   
 	// Now do the acquisition
 	i = 0;
@@ -995,6 +1275,7 @@ void T55xxReadTrace(void){
 	uint8_t *dest = (uint8_t *)BigBuf;
 	int m=0, i=0;
   
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	m = sizeof(BigBuf);
   // Clear destination buffer before sending the command
 	memset(dest, 128, m);
@@ -1005,7 +1286,7 @@ void T55xxReadTrace(void){
   
 	LED_D_ON();
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
   
 	// Give it a bit of time for the resonant antenna to settle.
 	// And for the tag to fully power up
@@ -1021,7 +1302,7 @@ void T55xxReadTrace(void){
   
   // Turn field on to read the response
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
   
 	// Now do the acquisition
 	i = 0;
@@ -1164,6 +1445,26 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
 	DbpString("DONE!");
 }
 
+void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
+{
+   int data1=0, data2=0; //up to six blocks for long format
+  	
+    data1 = hi;  // load preamble
+    data2 = lo;
+    
+    LED_D_ON();
+    // Program the data blocks for supplied ID
+    // and the block 0 for HID format
+    T55xxWriteBlock(data1,1,0,0);
+    T55xxWriteBlock(data2,2,0,0);
+	
+    //Config Block
+    T55xxWriteBlock(0x00147040,0,0,0);
+    LED_D_OFF();
+	
+    DbpString("DONE!");
+}
+
 // Define 9bit header for EM410x tags
 #define EM410X_HEADER		0x1FF
 #define EM410X_ID_LENGTH	40
@@ -1175,6 +1476,7 @@ void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
 	uint64_t rev_id = 0;	// reversed ID
 	int c_parity[4];	// column parity
 	int r_parity = 0;	// row parity
+	uint32_t clock = 0;
 
 	// Reverse ID bits given as parameter (for simpler operations)
 	for (i = 0; i < EM410X_ID_LENGTH; ++i) {
@@ -1232,12 +1534,35 @@ void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
 	T55xxWriteBlock((uint32_t)id, 2, 0, 0);
 
 	// Config for EM410x (RF/64, Manchester, Maxblock=2)
-	if (card)
+	if (card) {
+		// Clock rate is stored in bits 8-15 of the card value
+		clock = (card & 0xFF00) >> 8;
+		Dbprintf("Clock rate: %d", clock);
+		switch (clock)
+		{
+			case 32:
+				clock = T55x7_BITRATE_RF_32;
+				break;
+			case 16:
+				clock = T55x7_BITRATE_RF_16;
+				break;
+			case 0:
+				// A value of 0 is assumed to be 64 for backwards-compatibility
+				// Fall through...
+			case 64:
+				clock = T55x7_BITRATE_RF_64;
+				break;      
+			default:
+				Dbprintf("Invalid clock rate: %d", clock);
+				return;
+		}
+
 		// Writing configuration for T55x7 tag
-		T55xxWriteBlock(T55x7_BITRATE_RF_64	    |
+		T55xxWriteBlock(clock	    |
 				T55x7_MODULATION_MANCHESTER |
 				2 << T55x7_MAXBLOCK_SHIFT,
 				0, 0, 0);
+  }
 	else
 		// Writing configuration for T5555(Q5) tag
 		T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
@@ -1666,8 +1991,9 @@ void SendForward(uint8_t fwd_bit_count) {
   LED_D_ON();
   
   //Field on
+  FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
   
   // Give it a bit of time for the resonant antenna to settle.
   // And for the tag to fully power up
@@ -1679,7 +2005,7 @@ void SendForward(uint8_t fwd_bit_count) {
   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
   SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
   SpinDelayUs(16*8); //16 cycles on (8us each)
   
   // now start writting
@@ -1691,7 +2017,7 @@ void SendForward(uint8_t fwd_bit_count) {
       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
       SpinDelayUs(23*8); //16-4 cycles off (8us each)
       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-      FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
+      FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
       SpinDelayUs(9*8); //16 cycles on (8us each)
     }
   }