X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/6658905f18a1eebc148836f26c731dea9c1377dc..78d647da02c48dcdc4d93ee621f578aaa4d1c005:/fpga/fpga.v?ds=sidebyside diff --git a/fpga/fpga.v b/fpga/fpga.v index cbebc395..b22c9d5c 100644 --- a/fpga/fpga.v +++ b/fpga/fpga.v @@ -13,6 +13,7 @@ //----------------------------------------------------------------------------- `include "lo_read.v" +`include "lo_passthru.v" `include "lo_simulate.v" `include "hi_read_tx.v" `include "hi_read_rx_xcorr.v" @@ -21,7 +22,7 @@ `include "util.v" module fpga( - spck, miso, mosi, ncs, + spcki, miso, mosi, ncs, pck0i, ck_1356meg, ck_1356megb, pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4, adc_d, adc_clk, adc_noe, @@ -29,7 +30,7 @@ module fpga( cross_hi, cross_lo, dbg ); - input spck, mosi, ncs; + input spcki, mosi, ncs; output miso; input pck0i, ck_1356meg, ck_1356megb; output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4; @@ -40,11 +41,16 @@ module fpga( input cross_hi, cross_lo; output dbg; +//assign pck0 = pck0i; IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b( .O(pck0), .I(pck0i) ); -//assign pck0 = pck0i; +//assign spck = spcki; + IBUFG #(.IOSTANDARD("DEFAULT") ) spckb( + .O(spck), + .I(spcki) + ); //----------------------------------------------------------------------------- // The SPI receiver. This sets up the configuration word, which the rest of // the logic looks at to determine how to connect the A/D and the coil @@ -52,7 +58,8 @@ module fpga( // to the configuration bits, for use below. //----------------------------------------------------------------------------- -reg [7:0] conf_word_shift; +reg [15:0] shift_reg; +reg [7:0] divisor; reg [7:0] conf_word; // We switch modes between transmitting to the 13.56 MHz tag and receiving @@ -60,15 +67,18 @@ reg [7:0] conf_word; // glitching, or else we will glitch the transmitted carrier. always @(posedge ncs) begin - conf_word <= conf_word_shift; + case(shift_reg[15:12]) + 4'b0001: conf_word <= shift_reg[7:0]; + 4'b0010: divisor <= shift_reg[7:0]; + endcase end always @(posedge spck) begin if(~ncs) begin - conf_word_shift[7:1] <= conf_word_shift[6:0]; - conf_word_shift[0] <= mosi; + shift_reg[15:1] <= shift_reg[14:0]; + shift_reg[0] <= mosi; end end @@ -110,7 +120,16 @@ lo_read lr( lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk, cross_hi, cross_lo, lr_dbg, - lo_is_125khz + lo_is_125khz, divisor +); + +lo_passthru lp( + pck0, ck_1356meg, ck_1356megb, + lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4, + adc_d, lp_adc_clk, + lp_ssp_frame, lp_ssp_din, ssp_dout, lp_ssp_clk, + cross_hi, cross_lo, + lp_dbg, divisor ); lo_simulate ls( @@ -119,7 +138,7 @@ lo_simulate ls( adc_d, ls_adc_clk, ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk, cross_hi, cross_lo, - ls_dbg + ls_dbg, divisor ); hi_read_tx ht( @@ -169,20 +188,20 @@ hi_iso14443a hisn( // 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable // 100 -- HF simulated tag // 101 -- HF ISO14443-A -// 110 -- unused +// 110 -- LF passthrough // 111 -- everything off -mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, 1'b0, 1'b0); -mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, 1'b0, 1'b0); -mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, 1'b0, 1'b0); -mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, 1'b0, 1'b0); -mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, 1'b0, 1'b0); -mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, 1'b0, 1'b0); -mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, 1'b0, 1'b0); -mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, 1'b0, 1'b0); -mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, 1'b0, 1'b0); -mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, 1'b0, 1'b0); -mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, 1'b0, 1'b0); +mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, lp_ssp_clk, 1'b0); +mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, lp_ssp_din, 1'b0); +mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, lp_ssp_frame, 1'b0); +mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, lp_pwr_oe1, 1'b0); +mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, lp_pwr_oe2, 1'b0); +mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, lp_pwr_oe3, 1'b0); +mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, lp_pwr_oe4, 1'b0); +mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, lp_pwr_lo, 1'b0); +mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, lp_pwr_hi, 1'b0); +mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, lp_adc_clk, 1'b0); +mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, lp_dbg, 1'b0); // In all modes, let the ADC's outputs be enabled. assign adc_noe = 1'b0;