X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/72acba78844edd59c574d9c281c459eda0d9c1d5..e1c6e9e8f1d6e0266f79b5ec40a0bd93cd96b14a:/fpga/lo_passthru.v

diff --git a/fpga/lo_passthru.v b/fpga/lo_passthru.v
index 38142695..3507f660 100644
--- a/fpga/lo_passthru.v
+++ b/fpga/lo_passthru.v
@@ -1,35 +1,29 @@
-//-----------------------------------------------------------------------------
-// For reading TI tags, we need to place the FPGA in pass through mode
-// and pass everything through to the ARM
-//-----------------------------------------------------------------------------
-
-module lo_passthru(
-    pck0, ck_1356meg, ck_1356megb,
-    pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
-    adc_d, adc_clk,
-    ssp_frame, ssp_din, ssp_dout, ssp_clk,
-    cross_hi, cross_lo,
-    dbg
-);
-    input pck0, ck_1356meg, ck_1356megb;
-    output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
-    input [7:0] adc_d;
-    output adc_clk;
-    input ssp_dout;
-    output ssp_frame, ssp_din, ssp_clk;
-    input cross_hi, cross_lo;
-    output dbg;
-
-// No logic, straight through.
-
-assign pwr_oe3 = 1'b0;
-assign pwr_oe1 = 1'b1;
-assign pwr_oe2 = 1'b1;
-assign pwr_oe4 = 1'b1;
-assign pwr_lo = 1'b0;
-assign pwr_hi = 1'b0;
-assign adc_clk = 1'b0;
-assign ssp_din = cross_lo;
-assign dbg = cross_lo;
-
-endmodule
+//-----------------------------------------------------------------------------
+// For reading TI tags, we need to place the FPGA in pass through mode
+// and pass everything through to the ARM
+//-----------------------------------------------------------------------------
+// iZsh <izsh at fail0verflow.com>, June 2014
+
+module lo_passthru(
+	input pck_divclk,
+	output pwr_lo, output pwr_hi,
+	output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
+	output adc_clk,
+	output ssp_din, input ssp_dout,
+	input cross_lo,
+	output dbg
+);
+
+// the antenna is modulated when ssp_dout = 1, when 0 the
+// antenna drivers stop modulating and go into listen mode
+assign pwr_oe3 = 1'b0;
+assign pwr_oe1 = ssp_dout;
+assign pwr_oe2 = ssp_dout;
+assign pwr_oe4 = ssp_dout;
+assign pwr_lo = pck_divclk && ssp_dout;
+assign pwr_hi = 1'b0;
+assign adc_clk = 1'b0;
+assign ssp_din = cross_lo;
+assign dbg = cross_lo;
+
+endmodule