X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/7cc204bff881ce1d1833d8e93469f6bbba80c70e..b4c1f167da39e85f3d10757a1b615a64a6031f26:/fpga/lo_read.v

diff --git a/fpga/lo_read.v b/fpga/lo_read.v
index f2d79127..a6d077b9 100644
--- a/fpga/lo_read.v
+++ b/fpga/lo_read.v
@@ -4,6 +4,7 @@
 // The A/D samples at that same rate and the result is serialized.
 //
 // Jonathan Westhues, April 2006
+// iZsh <izsh at fail0verflow.com>, June 2014
 //-----------------------------------------------------------------------------
 
 module lo_read(
@@ -12,7 +13,8 @@ module lo_read(
 	output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
 	input [7:0] adc_d, output adc_clk,
 	output ssp_frame, output ssp_din, output ssp_clk,
-	output dbg
+	output dbg,
+	input lf_field
 );
 
 reg [7:0] to_arm_shiftreg;
@@ -64,7 +66,7 @@ assign pwr_oe2 = 1'b0;
 assign pwr_oe3 = 1'b0;
 assign pwr_oe4 = 1'b0;
 // this is the antenna driver signal
-assign pwr_lo = pck_divclk;
+assign pwr_lo = lf_field & pck_divclk;
 // ADC clock out of phase with antenna driver
 assign adc_clk = ~pck_divclk;
 // ADC clock also routed to debug pin