X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/a37228c8c26f32c3462f6b1641e64acddd62e0cc..6dd0ff3035ed40ab47f22d76dbc22942a492dca3:/armsrc/lfops.c

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index 35f220c0..36efe729 100644
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -4,7 +4,7 @@
 // the license.
 //-----------------------------------------------------------------------------
 // Miscellaneous routines for low frequency tag operations.
-// Tags supported here so far are Texas Instruments (TI), HID
+// Tags supported here so far are Texas Instruments (TI), HID, EM4x05, EM410x
 // Also routines for raw mode reading/simulating of LF waveform
 //-----------------------------------------------------------------------------
 
@@ -18,6 +18,7 @@
 #include "lfsampling.h"
 #include "protocols.h"
 #include "usb_cdc.h" // for usb_poll_validate_length
+#include "fpgaloader.h"
 
 /**
  * Function to do a modulation and then get samples.
@@ -28,51 +29,103 @@
  */
 void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint32_t period_1, uint8_t *command)
 {
+	// start timer
+	StartTicks();
 
-	int divisor_used = 95; // 125 KHz
-	// see if 'h' was specified
-
-	if (command[strlen((char *) command) - 1] == 'h')
-		divisor_used = 88; // 134.8 KHz
-
-	sample_config sc = { 0,0,1, divisor_used, 0};
-	setSamplingConfig(&sc);
-	//clear read buffer
-	BigBuf_Clear_keep_EM();
+	// use lf config settings
+	sample_config *sc = getSamplingConfig();
 
-	/* Make sure the tag is reset */
+	// Make sure the tag is reset
 	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelay(2500);
+	WaitMS(2500);
 
-	LFSetupFPGAForADC(sc.divisor, 1);
+	// clear read buffer (after fpga bitstream loaded...)
+	BigBuf_Clear_keep_EM();
 
-	// And a little more time for the tag to fully power up
-	SpinDelay(2000);
+	// power on
+	LFSetupFPGAForADC(sc->divisor, 1);
 
+	// And a little more time for the tag to fully power up
+	WaitMS(2000);
+	// if delay_off = 0 then just bitbang 1 = antenna on 0 = off for respective periods.
+	bool bitbang = delay_off == 0;
 	// now modulate the reader field
-	while(*command != '\0' && *command != ' ') {
+
+	if (bitbang) {
+		// HACK it appears the loop and if statements take up about 7us so adjust waits accordingly...
+		uint8_t hack_cnt = 7;
+		if (period_0 < hack_cnt || period_1 < hack_cnt) {
+			DbpString("Warning periods cannot be less than 7us in bit bang mode");
+			FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+			LED_D_OFF();
+			return;
+		}
+
+		// hack2 needed---  it appears to take about 8-16us to turn the antenna back on 
+		// leading to ~ 1 to 2 125khz samples extra in every off period 
+		// so we should test for last 0 before next 1 and reduce period_0 by this extra amount...
+		// but is this time different for every antenna or other hw builds???  more testing needed
+
+		// prime cmd_len to save time comparing strings while modulating
+		int cmd_len = 0;
+		while(command[cmd_len] != '\0' && command[cmd_len] != ' ')
+			cmd_len++;
+
+		int counter = 0;
+		bool off = false;
+		for (counter = 0; counter < cmd_len; counter++) {
+			// if cmd = 0 then turn field off
+			if (command[counter] == '0') {
+				// if field already off leave alone (affects timing otherwise)
+				if (off == false) {
+					FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+					LED_D_OFF();
+					off = true;
+				}
+				// note we appear to take about 7us to switch over (or run the if statements/loop...)
+				WaitUS(period_0-hack_cnt);
+			// else if cmd = 1 then turn field on
+			} else {
+				// if field already on leave alone (affects timing otherwise)
+				if (off) {
+					FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
+					LED_D_ON();
+					off = false;
+				}
+				// note we appear to take about 7us to switch over (or run the if statements/loop...)
+				WaitUS(period_1-hack_cnt);
+			}
+		}
+	} else { // old mode of cmd read using delay as off period
+		while(*command != '\0' && *command != ' ') {
+			FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+			LED_D_OFF();
+			WaitUS(delay_off);
+			FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc->divisor);
+			FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
+			LED_D_ON();
+			if(*(command++) == '0') {
+				WaitUS(period_0);
+			} else {
+				WaitUS(period_1);
+			}
+		}
 		FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 		LED_D_OFF();
-		SpinDelayUs(delay_off);
-		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
-
-		FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
-		LED_D_ON();
-		if(*(command++) == '0')
-			SpinDelayUs(period_0);
-		else
-			SpinDelayUs(period_1);
+		WaitUS(delay_off);
+		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc->divisor);
 	}
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	LED_D_OFF();
-	SpinDelayUs(delay_off);
-	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
 
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
 	// now do the read
-	DoAcquisition_config(false);
+	DoAcquisition_config(false, 0);
+
+	// Turn off antenna
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+	// tell client we are done
+	cmd_send(CMD_ACK,0,0,0,0,0);
 }
 
 /* blank r/w tag data stream
@@ -387,7 +440,8 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 	int i;
 	uint8_t *tab = BigBuf_get_addr();
 
-	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+	//note FpgaDownloadAndGo destroys the bigbuf so be sure this is called before now...
+	//FpgaDownloadAndGo(FPGA_BITSTREAM_LF);  
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
 
 	AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
@@ -401,13 +455,19 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 	i = 0;
 	for(;;) {
 		//wait until SSC_CLK goes HIGH
+		int ii = 0;
 		while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
-			if(BUTTON_PRESS() || (usb_poll_validate_length() )) {
-				FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-				DbpString("Stopped");
-				return;
+			//only check every 1000th time (usb_poll_validate_length on some systems was too slow)
+			if ( ii == 1000 ) {
+				if (BUTTON_PRESS() || usb_poll_validate_length() ) {
+					FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+					DbpString("Stopped");
+					return;
+				}
+				ii=0;
 			}
 			WDT_HIT();
+			ii++;
 		}
 		if (ledcontrol)
 			LED_D_ON();
@@ -419,14 +479,20 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 
 		if (ledcontrol)
 			LED_D_OFF();
+		ii=0;
 		//wait until SSC_CLK goes LOW
 		while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
-			if(BUTTON_PRESS() || (usb_poll_validate_length() )) {
-				DbpString("Stopped");
-				FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-				return;
+			//only check every 1000th time (usb_poll_validate_length on some systems was too slow)
+			if ( ii == 1000 ) { 
+				if (BUTTON_PRESS() || usb_poll_validate_length() ) {
+					FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+					DbpString("Stopped");
+					return;
+				}
+				ii=0;
 			}
 			WDT_HIT();
+			ii++;
 		}
 
 		i++;
@@ -503,7 +569,7 @@ static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
 	uint8_t wavesPerClock = clock/fc;
 	uint8_t mod = clock % fc;    //modifier
 	uint8_t modAdj = fc/mod;     //how often to apply modifier
-	bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
+	bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=true;
 	// loop through clock - step field clock
 	for (uint8_t idx=0; idx < wavesPerClock; idx++){
 		// put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
@@ -528,7 +594,7 @@ static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
 
 // prepare a waveform pattern in the buffer based on the ID given then
 // simulate a HID tag until the button is pressed
-void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
+void CmdHIDsimTAG(int hi2, int hi, int lo, int ledcontrol)
 {
 	int n=0, i=0;
 	/*
@@ -541,10 +607,13 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 	 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
 	*/
 
-	if (hi>0xFFF) {
-		DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
+	if (hi2>0x0FFFFFFF) {
+		DbpString("Tags can only have 44 or 84 bits. - USE lf simfsk for larger tags");
 		return;
 	}
+	// set LF so we don't kill the bigbuf we are setting with simulation data.
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+
 	fc(0,&n);
 	// special start of frame marker containing invalid bit sequences
 	fc(8,  &n);	fc(8,  &n); // invalid
@@ -553,13 +622,35 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 	fc(8,  &n);	fc(10, &n); // logical 0
 
 	WDT_HIT();
-	// manchester encode bits 43 to 32
-	for (i=11; i>=0; i--) {
-		if ((i%4)==3) fc(0,&n);
-		if ((hi>>i)&1) {
-			fc(10, &n); fc(8,  &n);		// low-high transition
-		} else {
-			fc(8,  &n); fc(10, &n);		// high-low transition
+	if (hi2 > 0 || hi > 0xFFF){
+		// manchester encode bits 91 to 64 (91-84 are part of the header)
+		for (i=27; i>=0; i--) {
+			if ((i%4)==3) fc(0,&n);
+			if ((hi2>>i)&1) {
+				fc(10, &n); fc(8,  &n);		// low-high transition
+			} else {
+				fc(8,  &n); fc(10, &n);		// high-low transition
+			}
+		}
+		WDT_HIT();
+		// manchester encode bits 63 to 32
+		for (i=31; i>=0; i--) {
+			if ((i%4)==3) fc(0,&n);
+			if ((hi>>i)&1) {
+				fc(10, &n); fc(8,  &n);		// low-high transition
+			} else {
+				fc(8,  &n); fc(10, &n);		// high-low transition
+			}
+		}
+	} else {
+		// manchester encode bits 43 to 32
+		for (i=11; i>=0; i--) {
+			if ((i%4)==3) fc(0,&n);
+			if ((hi>>i)&1) {
+				fc(10, &n); fc(8,  &n);		// low-high transition
+			} else {
+				fc(8,  &n); fc(10, &n);		// high-low transition
+			}
 		}
 	}
 
@@ -595,6 +686,9 @@ void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
 	uint8_t clk = arg2 & 0xFF;
 	uint8_t invert = (arg2 >> 8) & 1;
 
+	// set LF so we don't kill the bigbuf we are setting with simulation data.
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+
 	for (i=0; i<size; i++){
 		if (BitStream[i] == invert){
 			fcAll(fcLow, &n, clk, &modCnt);
@@ -670,6 +764,9 @@ void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
 	uint8_t separator = arg2 & 1;
 	uint8_t invert = (arg2 >> 8) & 1;
 
+	// set LF so we don't kill the bigbuf we are setting with simulation data.
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+
 	if (encoding==2){  //biphase
 		uint8_t phase=0;
 		for (i=0; i<size; i++){
@@ -741,11 +838,14 @@ void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
 	uint8_t carrier = arg1 & 0xFF;
 	uint8_t invert = arg2 & 0xFF;
 	uint8_t curPhase = 0;
+	// set LF so we don't kill the bigbuf we are setting with simulation data.
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+
 	for (i=0; i<size; i++){
 		if (BitStream[i] == curPhase){
-			pskSimBit(carrier, &n, clk, &curPhase, FALSE);
+			pskSimBit(carrier, &n, clk, &curPhase, false);
 		} else {
-			pskSimBit(carrier, &n, clk, &curPhase, TRUE);
+			pskSimBit(carrier, &n, clk, &curPhase, true);
 		}
 	}
 	Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
@@ -762,13 +862,14 @@ void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
 }
 
 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
-void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
+void CmdHIDdemodFSK(int findone, int *high2, int *high, int *low, int ledcontrol)
 {
 	uint8_t *dest = BigBuf_get_addr();
 	//const size_t sizeOfBigBuff = BigBuf_max_traceLen();
 	size_t size; 
 	uint32_t hi2=0, hi=0, lo=0;
 	int idx=0;
+	int dummyIdx = 0;
 	// Configure to go in 125Khz listen mode
 	LFSetupFPGAForADC(95, true);
 
@@ -776,7 +877,6 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 	BigBuf_Clear_keep_EM();
 
 	while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
-
 		WDT_HIT();
 		if (ledcontrol) LED_A_ON();
 
@@ -784,63 +884,73 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 		// FSK demodulator
 		//size = sizeOfBigBuff;  //variable size will change after demod so re initialize it before use
 		size = 50*128*2; //big enough to catch 2 sequences of largest format
-		idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
+		idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo, &dummyIdx);
 		
 		if (idx>0 && lo>0 && (size==96 || size==192)){
+			uint8_t bitlen = 0;
+			uint32_t fc = 0;
+			uint32_t cardnum = 0;
+			bool decoded = false;
+
 			// go over previously decoded manchester data and decode into usable tag ID
-			if (hi2 != 0){ //extra large HID tags  88/192 bits
-				Dbprintf("TAG ID: %x%08x%08x (%d)",
-				  (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-			}else {  //standard HID tags 44/96 bits
-				//Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
-				uint8_t bitlen = 0;
-				uint32_t fc = 0;
-				uint32_t cardnum = 0;
-				if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
-					uint32_t lo2=0;
-					lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
-					uint8_t idx3 = 1;
-					while(lo2 > 1){ //find last bit set to 1 (format len bit)
-						lo2=lo2 >> 1;
-						idx3++;
-					}
-					bitlen = idx3+19;
-					fc =0;
-					cardnum=0;
-					if(bitlen == 26){
-						cardnum = (lo>>1)&0xFFFF;
-						fc = (lo>>17)&0xFF;
-					}
-					if(bitlen == 37){
-						cardnum = (lo>>1)&0x7FFFF;
-						fc = ((hi&0xF)<<12)|(lo>>20);
-					}
-					if(bitlen == 34){
-						cardnum = (lo>>1)&0xFFFF;
-						fc= ((hi&1)<<15)|(lo>>17);
-					}
-					if(bitlen == 35){
-						cardnum = (lo>>1)&0xFFFFF;
-						fc = ((hi&1)<<11)|(lo>>21);
-					}
+			if ((hi2 & 0x000FFFF) != 0){ //extra large HID tags  88/192 bits
+				uint32_t bp = hi2 & 0x000FFFFF;
+				bitlen = 63;
+				while (bp > 0) {
+					bp = bp >> 1;
+					bitlen++;
 				}
-				else { //if bit 38 is not set then 37 bit format is used
-					bitlen= 37;
-					fc =0;
-					cardnum=0;
-					if(bitlen==37){
-						cardnum = (lo>>1)&0x7FFFF;
-						fc = ((hi&0xF)<<12)|(lo>>20);
-					}
+			} else if ((hi >> 6) > 0) {
+				uint32_t bp = hi;
+				bitlen = 31;
+				while (bp > 0) {
+					bp = bp >> 1;
+					bitlen++;
 				}
-				//Dbprintf("TAG ID: %x%08x (%d)",
-				// (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-				Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
-						 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
-						 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
+			} else if (((hi >> 5) & 1) == 0) {
+				bitlen = 37;
+			} else if ((hi & 0x0000001F) > 0 ) {
+				uint32_t bp = (hi & 0x0000001F);
+				bitlen = 31;
+				while (bp > 0) {
+					bp = bp >> 1;
+					bitlen++;
+				}
+			} else {
+				uint32_t bp = lo;
+				bitlen = 0;
+				while (bp > 0) {
+					bp = bp >> 1;
+					bitlen++;
+				}
+			}
+			switch (bitlen){
+				case 26:
+					cardnum = (lo>>1)&0xFFFF;
+					fc = (lo>>17)&0xFF;
+					decoded = true;
+					break;
+				case 35:
+					cardnum = (lo>>1)&0xFFFFF;
+					fc = ((hi&1)<<11)|(lo>>21);
+					decoded = true;
+					break;
 			}
+				
+			if (hi2 != 0) //extra large HID tags  88/192 bits
+				Dbprintf("TAG ID: %x%08x%08x (%d)",
+					(unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+			else 
+				Dbprintf("TAG ID: %x%08x (%d)",
+					(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+			
+			if (decoded)
+				Dbprintf("Format Len: %dbits - FC: %d - Card: %d",
+					(unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
+
 			if (findone){
 				if (ledcontrol)	LED_A_OFF();
+				*high2 = hi2;
 				*high = hi;
 				*low = lo;
 				break;
@@ -861,7 +971,7 @@ void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 {
 	uint8_t *dest = BigBuf_get_addr();
 	size_t size; 
-	int idx=0;
+	int idx=0, dummyIdx=0;
 	//clear read buffer
 	BigBuf_Clear_keep_EM();
 	// Configure to go in 125Khz listen mode
@@ -875,7 +985,7 @@ void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 		DoAcquisition_default(-1,true);
 		// FSK demodulator
 		size = 50*128*2; //big enough to catch 2 sequences of largest format
-		idx = AWIDdemodFSK(dest, &size);
+		idx = AWIDdemodFSK(dest, &size, &dummyIdx);
 		
 		if (idx<=0 || size!=96) continue;
 		// Index map
@@ -1017,6 +1127,7 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 	uint8_t version=0;
 	uint8_t facilitycode=0;
 	uint16_t number=0;
+	int dummyIdx=0;
 	//clear read buffer
 	BigBuf_Clear_keep_EM();
 	// Configure to go in 125Khz listen mode
@@ -1028,7 +1139,7 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 		DoAcquisition_default(-1,true);
 		//fskdemod and get start index
 		WDT_HIT();
-		idx = IOdemodFSK(dest, BigBuf_max_traceLen());
+		idx = IOdemodFSK(dest, BigBuf_max_traceLen(), &dummyIdx);
 		if (idx<0) continue;
 		//valid tag found
 
@@ -1092,11 +1203,13 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 #define WRITE_0   18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
 #define WRITE_1   50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc)  432 for T55x7; 448 for E5550
 #define READ_GAP  15*8 
+// Long Leading Reference
+#define Reference_llr (136+18)*8  // Needs to be WRITR_0 + 136 clocks.
 
 void TurnReadLFOn(int delay) {
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 	// Give it a bit of time for the resonant antenna to settle.
-	SpinDelayUs(delay); //155*8 //50*8
+	WaitUS(delay); //155*8 //50*8
 }
 
 // Write one bit to card
@@ -1106,7 +1219,266 @@ void T55xxWriteBit(int bit) {
 	else
 		TurnReadLFOn(WRITE_1);
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelayUs(WRITE_GAP);
+	WaitUS(WRITE_GAP);
+}
+
+void T55xxWrite_LLR (void)
+{
+	TurnReadLFOn (Reference_llr);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+	WaitUS(WRITE_GAP);	
+}
+
+#define START_GAPlz 31*8 
+#define WRITE_GAPlz 20*8 
+#define WRITElz_0   18*8 
+#define WRITElz_1   40*8 
+#define READ_GAP  15*8 
+
+void T55xxWriteBit_Leading0(int bit) {
+	if (!bit)
+		TurnReadLFOn(WRITElz_0);
+	else
+		TurnReadLFOn(WRITElz_1);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+	WaitUS(WRITE_GAPlz);
+//	WaitUS(160);
+}
+
+#define START_GAP1of4 31*8 // SPEC:  1*8 to 50*8 - typ 10*8 (or 15fc)
+#define WRITE_GAP1of4 20*8 // SPEC:  1*8 to 20*8 - typ 10*8 (or 10fc)
+//  00 = reference			// 8 * 8 -  - 68 * 8
+#define WRITE1of4_00  18*8 // SPEC:  8*8 to 68*8 - typ 24*8 (or 24fc)
+#define WRITE1of4_01  34*8 // SPEC: dref+9  - dref+16 - dref+24 
+#define WRITE1of4_10  50*8 // SPEC: dref+25 - dref+32 - dref+40
+#define WRITE1of4_11  66*8 // SPEC: dref+41 - dref+48 - dref+56
+#define READ1of4_GAP  15*8 
+
+void T55xxWriteBit_1of4(int bits) {
+	
+	switch (bits)
+	{
+		case 0 :  TurnReadLFOn(WRITE1of4_00); break;
+		case 1 :  TurnReadLFOn(WRITE1of4_01); break;
+		case 2 :  TurnReadLFOn(WRITE1of4_10); break;
+		case 3 :  TurnReadLFOn(WRITE1of4_11); break;
+		default:
+			TurnReadLFOn(WRITE1of4_00);
+	}		
+
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+	WaitUS(WRITE_GAP1of4);
+//	WaitUS(160);
+}
+
+void T55xxWriteBlockExt_Leading0 (uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
+
+	LED_A_ON();
+	bool PwdMode = arg & 0x1;
+	uint8_t Page = (arg & 0x2)>>1;
+	bool testMode = arg & 0x4;
+	uint32_t i = 0;
+	
+	// Set up FPGA, 125kHz
+	LFSetupFPGAForADC(95, true);
+	StartTicks();
+	// make sure tag is fully powered up...
+	WaitMS(5);
+	// Trigger T55x7 in mode.
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+
+	WaitUS(START_GAPlz);
+	
+	
+	/* 
+	   0 	: Leading Zero
+	   11   : Opcode
+	   00   : Fixed 00 if protected write (i.e. have password)
+	   <32 bit Password>
+	   0 	: Lock Bit
+	   <32 bit data> 
+	   <3 bit addr>
+
+	   	Standard Write : 0 1p L <32 data bits> <3 bit addr>
+		                 0 10 0 00000000000000000000000000000000 001
+		Protected Write: 0 1p 00 <32 pwd bits> L <32 data bits> <3 bit addr>
+					     0 10 00 00000000000000000000000000000000 0 00000000000000000000000000000000 001
+		Wake Up			 0 10 00 <32 pwd bits>
+		Protected Read   0 1p 00 <32 pwd bits> 0 <3 bit addr>
+		Standard Read    0 1p 0 <3 bit addr>
+		Page 0/1 read    0 1p
+		Reset            0 00
+		
+	*/
+		T55xxWriteBit_Leading0 (0); //T55xxWriteBit(0);
+				
+	
+		if (testMode) Dbprintf("TestMODE");
+			// Std Opcode 10
+			T55xxWriteBit_Leading0 (testMode ? 0 : 1);
+			T55xxWriteBit_Leading0 (testMode ? 1 : Page); //Page 0
+		
+	
+		if (PwdMode) {
+			// Leading zero - insert two fixed 00 between opcode and password
+			T55xxWriteBit_Leading0 (0);
+			T55xxWriteBit_Leading0 (0);
+			// Send Pwd
+			for (i = 0x80000000; i != 0; i >>= 1)
+				T55xxWriteBit_Leading0 (Pwd & i);
+		}
+	
+		// Send Lock bit
+		T55xxWriteBit_Leading0 (0);
+
+		// Send Data
+		for (i = 0x80000000; i != 0; i >>= 1)
+			T55xxWriteBit_Leading0(Data & i);
+
+		// Send Block number
+		for (i = 0x04; i != 0; i >>= 1)
+			T55xxWriteBit_Leading0 (Block & i);
+			
+		// Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
+		// so wait a little more)
+		// "there is a clock delay before programming" 
+		//  - programming takes ~5.6ms for t5577 ~18ms for E5550 or t5567
+		//  so we should wait 1 clock + 5.6ms then read response? 
+		//  but we need to know we are dealing with t5577 vs t5567 vs e5550 (or q5) marshmellow...
+		if (testMode) {
+			//TESTMODE TIMING TESTS: 
+			// <566us does nothing 
+			// 566-568 switches between wiping to 0s and doing nothing
+			// 5184 wipes and allows 1 block to be programmed.
+			// indefinite power on wipes and then programs all blocks with bitshifted data sent.
+			TurnReadLFOn(5184); 
+
+		} else {
+			TurnReadLFOn(20 * 1000);
+			//could attempt to do a read to confirm write took
+			// as the tag should repeat back the new block 
+			// until it is reset, but to confirm it we would 
+			// need to know the current block 0 config mode for
+			// modulation clock an other details to demod the response...
+			// response should be (for t55x7) a 0 bit then (ST if on) 
+			// block data written in on repeat until reset. 
+
+			//DoPartialAcquisition(20, true, 12000);
+		}
+
+		// turn field off
+		FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+		LED_A_OFF();
+	
+}
+void T55xxWriteBlockExt_1of4 (uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
+
+	LED_A_ON();
+    bool PwdMode = arg & 0x1;
+	uint8_t Page = (arg & 0x2)>>1;
+	bool testMode = arg & 0x4;
+	int bitpos;
+	uint8_t bits;
+	
+	// Set up FPGA, 125kHz
+	LFSetupFPGAForADC(95, true);
+	StartTicks();
+	// make sure tag is fully powered up...
+	WaitMS(5);
+	// Trigger T55x7 in mode.
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+
+	
+	WaitUS(START_GAP1of4);
+	
+	
+	/* 
+	   00 	: 1 if 4
+	   11   : Opcode
+	   00   : Fixed 00 if protected write (i.e. have password)
+	   <32 bit Password>
+	   0 	: Lock Bit
+	   <32 bit data> 
+	   <3 bit addr>
+
+	   	Standard Write : 00 1p L <32 data bits> <3 bit addr>
+		                 00 10 0 00000000000000000000000000000000 001
+		Protected Write: 00 1p 00 <32 pwd bits> L <32 data bits> <3 bit addr>
+					     00 10 00 00000000000000000000000000000000 0 00000000000000000000000000000000 001
+		Wake Up			 00 10 00 <32 pwd bits>
+		Protected Read   00 1p 00 <32 pwd bits> 0 <3 bit addr>
+		Standard Read    00 1p 0 <3 bit addr>
+		Page 0/1 read    00 1p
+		Reset            00 00
+		
+	*/
+		T55xxWriteBit_1of4 (0); //Send Reference 00
+	
+		if (testMode) Dbprintf("TestMODE");
+		// Std Opcode 10
+		if (testMode) bits  = 0; else bits   = 2;			// 0x or 1x
+		if (testMode) bits |= 1; else bits  += (Page);  //  x0 or x1
+		T55xxWriteBit_1of4 (bits);
+		
+		if (PwdMode) {
+			// 1 of 4 00 - insert two fixed 00 between opcode and password
+			T55xxWriteBit_1of4 (0); // 00
+			
+			// Send Pwd
+			for (bitpos = 31; bitpos >= 1; bitpos -= 2) { // 2 bits at a time
+				bits = (((Pwd >> bitpos) & 1) << 1) + ((Pwd >> (bitpos-1)) & 1);	
+				T55xxWriteBit_1of4 (bits);
+			}
+		}
+		
+		// Send Lock bit
+		bits = 0; // Add lock bit (Not Set) to the next 2 bits
+	
+		// Send Data - offset by 1 bit due to lock bit
+		// 2 bits at a time - Initilised with lock bit above
+		for (bitpos = 31; bitpos >= 1; bitpos -= 2) { 
+				bits  |= ((Data >> bitpos) & 1);  // Add Low bit
+				T55xxWriteBit_1of4 (bits);
+				bits = ((Data >> (bitpos-1)) & 1) << 1; // Set next high bit 	
+		}
+
+		// Send Block number
+		bits  |= ((Block >> 2) & 1); 
+		T55xxWriteBit_1of4 (bits);
+		bits = (Block & 3);// 1) & 2) + (Block & 1);
+		T55xxWriteBit_1of4 (bits);			
+			
+		// Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
+		// so wait a little more)
+		// "there is a clock delay before programming" 
+		//  - programming takes ~5.6ms for t5577 ~18ms for E5550 or t5567
+		//  so we should wait 1 clock + 5.6ms then read response? 
+		//  but we need to know we are dealing with t5577 vs t5567 vs e5550 (or q5) marshmellow...
+		if (testMode) {
+			//TESTMODE TIMING TESTS: 
+			// <566us does nothing 
+			// 566-568 switches between wiping to 0s and doing nothing
+			// 5184 wipes and allows 1 block to be programmed.
+			// indefinite power on wipes and then programs all blocks with bitshifted data sent.
+			TurnReadLFOn(5184); 
+
+		} else {
+			TurnReadLFOn(20 * 1000);
+			//could attempt to do a read to confirm write took
+			// as the tag should repeat back the new block 
+			// until it is reset, but to confirm it we would 
+			// need to know the current block 0 config mode for
+			// modulation clock an other details to demod the response...
+			// response should be (for t55x7) a 0 bit then (ST if on) 
+			// block data written in on repeat until reset. 
+
+			//DoPartialAcquisition(20, true, 12000);
+		}
+
+		// turn field off
+		FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+		LED_A_OFF();
+	
 }
 
 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
@@ -1117,20 +1489,22 @@ void T55xxResetRead(void) {
 
 	// Set up FPGA, 125kHz
 	LFSetupFPGAForADC(95, true);
-
+	StartTicks();
+	// make sure tag is fully powered up...
+	WaitMS(5);
+	
 	// Trigger T55x7 in mode.
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelayUs(START_GAP);
+	WaitUS(START_GAP);
 
 	// reset tag - op code 00
 	T55xxWriteBit(0);
 	T55xxWriteBit(0);
 
-	// Turn field on to read the response
 	TurnReadLFOn(READ_GAP);
 
 	// Acquisition
-	doT55x7Acquisition(BigBuf_max_traceLen());
+	DoPartialAcquisition(0, true, BigBuf_max_traceLen(), 0);
 
 	// Turn the field off
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
@@ -1143,19 +1517,24 @@ void T55xxWriteBlockExt(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg
 	LED_A_ON();
 	bool PwdMode = arg & 0x1;
 	uint8_t Page = (arg & 0x2)>>1;
+	bool testMode = arg & 0x4;
 	uint32_t i = 0;
 
 	// Set up FPGA, 125kHz
 	LFSetupFPGAForADC(95, true);
-
+	StartTicks();
+	// make sure tag is fully powered up...
+	WaitMS(5);
 	// Trigger T55x7 in mode.
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelayUs(START_GAP);
+	WaitUS(START_GAP);
 
-	// Opcode 10
-	T55xxWriteBit(1);
-	T55xxWriteBit(Page); //Page 0
-	if (PwdMode){
+	if (testMode) Dbprintf("TestMODE");
+	// Std Opcode 10
+	T55xxWriteBit(testMode ? 0 : 1);
+	T55xxWriteBit(testMode ? 1 : Page); //Page 0
+
+	if (PwdMode) {
 		// Send Pwd
 		for (i = 0x80000000; i != 0; i >>= 1)
 			T55xxWriteBit(Pwd & i);
@@ -1173,11 +1552,31 @@ void T55xxWriteBlockExt(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg
 
 	// Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
 	// so wait a little more)
-	TurnReadLFOn(20 * 1000);
+
+	// "there is a clock delay before programming" 
+	//  - programming takes ~5.6ms for t5577 ~18ms for E5550 or t5567
+	//  so we should wait 1 clock + 5.6ms then read response? 
+	//  but we need to know we are dealing with t5577 vs t5567 vs e5550 (or q5) marshmellow...
+	if (testMode) {
+		//TESTMODE TIMING TESTS: 
+		// <566us does nothing 
+		// 566-568 switches between wiping to 0s and doing nothing
+		// 5184 wipes and allows 1 block to be programmed.
+		// indefinite power on wipes and then programs all blocks with bitshifted data sent.
+		TurnReadLFOn(5184); 
+
+	} else {
+		TurnReadLFOn(20 * 1000);
 		//could attempt to do a read to confirm write took
 		// as the tag should repeat back the new block 
 		// until it is reset, but to confirm it we would 
-		// need to know the current block 0 config mode
+		// need to know the current block 0 config mode for
+		// modulation clock an other details to demod the response...
+		// response should be (for t55x7) a 0 bit then (ST if on) 
+		// block data written in on repeat until reset. 
+
+		//DoPartialAcquisition(20, true, 12000);
+	}
 
 	// turn field off
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
@@ -1186,17 +1585,39 @@ void T55xxWriteBlockExt(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg
 
 // Write one card block in page 0, no lock
 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
-	T55xxWriteBlockExt(Data, Block, Pwd, arg);
+//	arg 8 bit 00000000 
+//            0000000x	Password
+//            000000x0  Page
+//            00000x00  Test Mode
+//            000xx000  (0x18) where xx : 00 - Normal Write, 01 - Long Leading Reference
+//										  10 - Leading 0,    11 - 1 of 4
+	uint8_t downlink_mode;
+	
+	downlink_mode = (arg >> 3) & 0x03;
+	
+	switch (downlink_mode)
+	{
+		case 0 :	T55xxWriteBlockExt          (Data, Block, Pwd, arg);	break;
+		case 1 :    T55xxWrite_LLR ();
+					T55xxWriteBlockExt          (Data, Block, Pwd, arg);
+					break;
+		case 2 :	T55xxWriteBlockExt_Leading0 (Data, Block, Pwd, arg); 	break;
+		case 3 :	T55xxWriteBlockExt_1of4     (Data, Block, Pwd, arg); 	break;
+		
+		default:
+				T55xxWriteBlockExt    (Data, Block, Pwd, arg);
+	}					
+
 	cmd_send(CMD_ACK,0,0,0,0,0);
 }
 
 // Read one card block in page [page]
-void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
+void T55xxReadBlockExt (uint16_t arg0, uint8_t Block, uint32_t Pwd) {
 	LED_A_ON();
 	bool PwdMode = arg0 & 0x1;
 	uint8_t Page = (arg0 & 0x2) >> 1;
 	uint32_t i = 0;
-	bool RegReadMode = (Block == 0xFF);
+	bool RegReadMode = (Block == 0xFF);//regular read mode
 
 	//clear buffer now so it does not interfere with timing later
 	BigBuf_Clear_ext(false);
@@ -1206,10 +1627,12 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
 
 	// Set up FPGA, 125kHz to power up the tag
 	LFSetupFPGAForADC(95, true);
-
+	StartTicks();
+	// make sure tag is fully powered up...
+	WaitMS(5);
 	// Trigger T55x7 Direct Access Mode with start gap
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelayUs(START_GAP);
+	WaitUS(START_GAP);
 
 	// Opcode 1[page]
 	T55xxWriteBit(1);
@@ -1229,27 +1652,186 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
 			T55xxWriteBit(Block & i);		
 
 	// Turn field on to read the response
-	TurnReadLFOn(READ_GAP);
+	// 137*8 seems to get to the start of data pretty well... 
+	//  but we want to go past the start and let the repeating data settle in...
+	TurnReadLFOn(210*8); 
 
 	// Acquisition
-	doT55x7Acquisition(12000);
+	// Now do the acquisition
+	DoPartialAcquisition(0, true, 12000, 0);
 
 	// Turn the field off
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
-	cmd_send(CMD_ACK,0,0,0,0,0);    
+//	cmd_send(CMD_ACK,0,0,0,0,0);    
 	LED_A_OFF();
 }
 
+void T55xxReadBlockExt_Leading0 (uint16_t arg0, uint8_t Block, uint32_t Pwd) {
+	LED_A_ON();
+	bool     PwdMode = arg0 & 0x1;
+	uint8_t  Page    = (arg0 & 0x2) >> 1;
+	uint32_t i       = 0;
+	bool RegReadMode = (Block == 0xFF);//regular read mode
+	 
+	//clear buffer now so it does not interfere with timing later
+	BigBuf_Clear_ext(false);
+
+	//make sure block is at max 7
+	Block &= 0x7;
+
+	// Set up FPGA, 125kHz to power up the tag
+	LFSetupFPGAForADC(95, true);
+	StartTicks();
+	// make sure tag is fully powered up...
+	WaitMS(5);
+	// Trigger T55x7 Direct Access Mode with start gap
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+	WaitUS(START_GAPlz);
+
+	T55xxWriteBit_Leading0 (0); 
+
+	// Opcode 1[page]
+	T55xxWriteBit_Leading0 (1);
+	T55xxWriteBit_Leading0 (Page); //Page 0
+
+	if (PwdMode){
+		// Send Pwd
+		T55xxWriteBit_Leading0 (0);
+		T55xxWriteBit_Leading0 (0);		
+		
+		for (i = 0x80000000; i != 0; i >>= 1)
+			T55xxWriteBit_Leading0 (Pwd & i);
+	}
+	// Send a zero bit separation
+	T55xxWriteBit_Leading0(0);
+
+	// Send Block number (if direct access mode)
+	if (!RegReadMode)
+		for (i = 0x04; i != 0; i >>= 1)
+			T55xxWriteBit_Leading0(Block & i);		
+
+	// Turn field on to read the response
+	// 137*8 seems to get to the start of data pretty well... 
+	//  but we want to go past the start and let the repeating data settle in...
+	TurnReadLFOn(210*8); 
+
+	// Acquisition
+	// Now do the acquisition
+	DoPartialAcquisition(0, true, 12000, 0);
+
+	// Turn the field off
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+//	cmd_send(CMD_ACK,0,0,0,0,0);    
+	LED_A_OFF();
+}
+
+void T55xxReadBlockExt_1of4 (uint16_t arg0, uint8_t Block, uint32_t Pwd) {
+	LED_A_ON();
+	bool     PwdMode = arg0 & 0x1;
+	uint8_t  Page    = (arg0 & 0x2) >> 1;
+	//uint32_t i       = 0;
+	bool RegReadMode = (Block == 0xFF);//regular read mode
+	uint8_t bits;
+	int bitpos;
+	 
+	//clear buffer now so it does not interfere with timing later
+	BigBuf_Clear_ext(false);
+
+	//make sure block is at max 7
+	Block &= 0x7;
+
+	// Set up FPGA, 125kHz to power up the tag
+	LFSetupFPGAForADC(95, true);
+	StartTicks();
+	// make sure tag is fully powered up...
+	WaitMS(5);
+	// Trigger T55x7 Direct Access Mode with start gap
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+	WaitUS(START_GAP1of4);
+
+	T55xxWriteBit_1of4 (0); // 2 Bit 00 leading reference 
+
+	// Opcode 1[page]
+	bits = 2 + Page;
+	T55xxWriteBit_1of4 (bits);
+	
+	if (PwdMode) {
+		// 1 of 4 00 - insert two fixed 00 between opcode and password
+		T55xxWriteBit_1of4 (0); // 00
+		
+		// Send Pwd
+		for (bitpos = 31; bitpos >= 1; bitpos -= 2) { // 2 bits at a time
+			bits = (((Pwd >> bitpos) & 1) << 1) + ((Pwd >> (bitpos-1)) & 1);	
+			T55xxWriteBit_1of4 (bits);
+		}
+	}
+	
+	// Send Lock bit
+	bits = 0; // Add lock bit (Not Set) to the next 2 bits
+
+	// Send Block number (if direct access mode)
+	if (!RegReadMode){
+		// Send Block number
+		bits  += ((Block >> 2) & 1); 
+		T55xxWriteBit_1of4 (bits);
+		bits = (Block & 3); //  + (Block & 1);
+		T55xxWriteBit_1of4 (bits);				
+	}	
+
+	// Turn field on to read the response
+	// 137*8 seems to get to the start of data pretty well... 
+	//  but we want to go past the start and let the repeating data settle in...
+	TurnReadLFOn(210*8); 
+
+	// Acquisition
+	// Now do the acquisition
+	DoPartialAcquisition(0, true, 12000, 0);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+//	cmd_send(CMD_ACK,0,0,0,0,0);    
+	LED_A_OFF();
+}
+
+void T55xxReadBlock (uint16_t arg0, uint8_t Block, uint32_t Pwd) {
+//	arg0 16 bit 00000000 
+//              0000000x  Password
+//              000000x0  Page
+//              00000x00  
+//              000xx000  (0x18) where xx : 00 - Normal Write, 01 - Long Leading Reference
+//										    10 - Leading 0,    11 - 1 of 4
+	uint8_t downlink_mode;
+	
+	downlink_mode = (arg0 >> 3) & 0x03;
+
+	//  downlink mode id set to match the 2 bit as per Tech Sheet
+	switch (downlink_mode)
+	{
+		case 0 :	T55xxReadBlockExt 			(arg0, Block, Pwd); 	break;
+		case 1 :  	T55xxWrite_LLR ();
+					T55xxReadBlockExt 			(arg0, Block, Pwd);
+				    break;
+		case 2 :	T55xxReadBlockExt_Leading0 	(arg0, Block, Pwd); 	break;
+		case 3 :	T55xxReadBlockExt_1of4		(arg0, Block, Pwd);		break;
+		default:
+					T55xxReadBlockExt           (arg0, Block, Pwd) ;
+	}					
+
+//	T55xxReadBlockExt           (arg0, Block, Pwd) ;
+	cmd_send(CMD_ACK,0,0,0,0,0);
+}
+
 void T55xxWakeUp(uint32_t Pwd){
 	LED_B_ON();
 	uint32_t i = 0;
 	
 	// Set up FPGA, 125kHz
 	LFSetupFPGAForADC(95, true);
+	StartTicks();
+	// make sure tag is fully powered up...
+	WaitMS(5);
 	
 	// Trigger T55x7 Direct Access Mode
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelayUs(START_GAP);
+	WaitUS(START_GAP);
 	
 	// Opcode 10
 	T55xxWriteBit(1);
@@ -1272,8 +1854,8 @@ void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
 	}
 }
 
-// Copy HID id to card and setup block 0 config
-void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
+// Copy a HID-like card (e.g. HID Proximity, Paradox) to a T55x7 compatible card
+void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT, uint8_t preamble) {
 	uint32_t data[] = {0,0,0,0,0,0,0};
 	uint8_t last_block = 0;
 
@@ -1285,15 +1867,15 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
 		}
 		// Build the 6 data blocks for supplied 84bit ID
 		last_block = 6;
-		// load preamble (1D) & long format identifier (9E manchester encoded)
-		data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
+		// load preamble & long format identifier (9E manchester encoded)
+		data[1] = (preamble << 24) | 0x96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
 		// load raw id from hi2, hi, lo to data blocks (manchester encoded)
 		data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
 		data[3] = manchesterEncode2Bytes(hi >> 16);
 		data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
 		data[5] = manchesterEncode2Bytes(lo >> 16);
 		data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
-	}	else {
+	} else {
 		// Ensure no more than 44 bits supplied
 		if (hi>0xFFF) {
 			DbpString("Tags can only have 44 bits.");
@@ -1302,7 +1884,7 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
 		// Build the 3 data blocks for supplied 44bit ID
 		last_block = 3;
 		// load preamble
-		data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
+		data[1] = (preamble << 24) | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
 		data[2] = manchesterEncode2Bytes(lo >> 16);
 		data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
 	}
@@ -1355,10 +1937,10 @@ void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t
 	//Program the 7 data blocks for supplied 224bit UID
 	uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
 	// and the block 0 for Indala224 format	
-	//Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
-	data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
+	//Config for Indala (RF/32;PSK2 with RF/2;Maxblock=7)
+	data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK2 | (7 << T55x7_MAXBLOCK_SHIFT);
 	//TODO add selection of chip for Q5 or T55x7
-	// data[0] = (((32-2)>>1)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
+	// data[0] = (((32-2)>>1)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK2 | 7 << T5555_MAXBLOCK_SHIFT;
 	WriteT55xx(data, 0, 8);
 	//Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
 	//	T5567WriteBlock(0x603E10E2,0);
@@ -1367,7 +1949,7 @@ void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t
 // clone viking tag to T55xx
 void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
 	uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
-	if (Q5) data[0] = ( ((32-2)>>1) << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
+	if (Q5) data[0] = T5555_SET_BITRATE(32) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
 	// Program the data blocks for supplied ID and the block 0 config
 	WriteT55xx(data, 0, 3);
 	LED_D_OFF();
@@ -1451,8 +2033,7 @@ void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
 		}
 		data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
 	} else { //t5555 (Q5)
-		clock = (clock-2)>>1;  //n = (RF-2)/2
-		data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
+		data[0] = T5555_SET_BITRATE(clock) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
 	}
 
 	WriteT55xx(data, 0, 3);
@@ -1571,27 +2152,27 @@ void SendForward(uint8_t fwd_bit_count) {
 	fwd_write_ptr = forwardLink_data;
 	fwd_bit_sz = fwd_bit_count;
 
-	// Set up FPGA, 125kHz
+	// Set up FPGA, 125kHz or 95 divisor
 	LFSetupFPGAForADC(95, true);
 
 	// force 1st mod pulse (start gap must be longer for 4305)
 	fwd_bit_sz--; //prepare next bit modulation
 	fwd_write_ptr++;
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
-	SpinDelayUs(56*8); //55 cycles off (8us each)for 4305  /another reader has 37 here...
+	WaitUS(55*8); //55 cycles off (8us each)for 4305  //another reader has 37 here...
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
-	SpinDelayUs(18*8); //16 cycles on (8us each)  // another reader has 18 here
+	WaitUS(18*8); //18 cycles on (8us each)
 
 	// now start writting
 	while(fwd_bit_sz-- > 0) { //prepare next bit modulation
 		if(((*fwd_write_ptr++) & 1) == 1)
-			SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
+			WaitUS(32*8); //32 cycles at 125Khz (8us each)
 		else {
 			//These timings work for 4469/4269/4305 (with the 55*8 above)
 			FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
-			SpinDelayUs(23*8); //16-4 cycles off (8us each) //23  //one reader goes as high as 25 here
+			WaitUS(23*8); //23 cycles off (8us each)
 			FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
-			SpinDelayUs(16*8); //16 cycles on (8us each) //9  // another reader goes to 17 here
+			WaitUS(18*8); //18 cycles on (8us each)
 		}
 	}
 }
@@ -1618,6 +2199,7 @@ void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
 	BigBuf_Clear_ext(false);
 
 	LED_A_ON();
+	StartTicks();
 	//If password mode do login
 	if (PwdMode == 1) EM4xLogin(Pwd);
 
@@ -1626,9 +2208,9 @@ void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
 	fwd_bit_count += Prepare_Addr( Address );
 
 	SendForward(fwd_bit_count);
-
+	WaitUS(400);
 	// Now do the acquisition
-	DoPartialAcquisition(20, true, 5500);
+	DoPartialAcquisition(20, true, 6000, 1000);
 	
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
 	LED_A_OFF();
@@ -1645,6 +2227,7 @@ void EM4xWriteWord(uint32_t flag, uint32_t Data, uint32_t Pwd) {
 	BigBuf_Clear_ext(false);
 
 	LED_A_ON();
+	StartTicks();
 	//If password mode do login
 	if (PwdMode) EM4xLogin(Pwd);
 
@@ -1658,8 +2241,9 @@ void EM4xWriteWord(uint32_t flag, uint32_t Data, uint32_t Pwd) {
 	//Wait for write to complete
 	//SpinDelay(10);
 
+	WaitUS(6500);
 	//Capture response if one exists
-	DoPartialAcquisition(20, true, 5500);
+	DoPartialAcquisition(20, true, 6000, 1000);
 
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
 	LED_A_OFF();
@@ -1702,7 +2286,7 @@ void Cotag(uint32_t arg0) {
 	SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
 
 	// Now set up the SSC to get the ADC samples that are now streaming at us.
-	FpgaSetupSsc();
+	FpgaSetupSsc(FPGA_MAJOR_MODE_LF_ADC);
 
 	// start clock - 1.5ticks is 1us
 	StartTicks();
@@ -1716,7 +2300,7 @@ void Cotag(uint32_t arg0) {
 	switch(rawsignal) {
 		case 0: doCotagAcquisition(50000); break;
 		case 1: doCotagAcquisitionManchester(); break;
-		case 2: DoAcquisition_config(TRUE); break;
+		case 2: DoAcquisition_config(true, 0); break;
 	}
 
 	// Turn the field off