X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/ab3af4fe8510c66c8fba51b91fbf0f31a85220fe..f72669f366f07210befb8e21e711204e592dae37:/armsrc/util.c

diff --git a/armsrc/util.c b/armsrc/util.c
index 1efc2b2b..37fe3f43 100644
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -56,7 +56,7 @@ uint32_t reflect(uint32_t v, int b) {
 			v |=  BITMASK((b-1)-i);
 		else
 			v &= ~BITMASK((b-1)-i);
-		t>>=1;
+		t >>= 1;
 	}
 	return v;
 }
@@ -340,16 +340,25 @@ void StartCountUS() {
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable  
 	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
 	
-	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
-	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 	AT91C_BASE_TCB->TCB_BCR = 1;
-	}
+	
+	while (AT91C_BASE_TC1->TC_CV >= 1);
+}
 
 uint32_t RAMFUNC GetCountUS(){
 	//return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
 	//  By suggestion from PwPiwi, http://www.proxmark.org/forum/viewtopic.php?pid=17548#p17548
 	//return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3); 
 	return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV << 1) / 3); 
+	//return (AT91C_BASE_TC1->TC_CV << 16) | ((AT91C_BASE_TC0->TC_CV << 1) / 3); 
+}
+void ResetUSClock(void) {	
+	//enable clock of timer and software trigger
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+	while (AT91C_BASE_TC1->TC_CV >= 1);
 }
 
 // static uint32_t GlobalUsCounter = 0;
@@ -400,9 +409,9 @@ void StartCountSspClk() {
 							| AT91C_TC_WAVE 				// Waveform Mode
 							| AT91C_TC_WAVESEL_UP;	 		// just count
 
-	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;				// enable TC0
-	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;				// enable TC1
-	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;				// enable TC2
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;				// enable and reset TC0
+	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;				// enable and reset TC1
+	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;				// enable and reset TC2
 
 	// synchronize the counter with the ssp_frame signal. 
 	// Note: FPGA must be in any iso14443 mode, otherwise the frame signal would not be present 
@@ -420,7 +429,13 @@ void StartCountSspClk() {
 
 	// The high word of the counter (TC2) will not reset until the low word (TC0) overflows. 
 	// Therefore need to wait quite some time before we can use the counter.
-	while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
+	while (AT91C_BASE_TC2->TC_CV >= 1);
+}
+void ResetSspClk(void) {	
+	//enable clock of timer and software trigger
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 }
 
 uint32_t RAMFUNC GetCountSspClk(){