X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/be59094de9527e0e935d6d1cdd445d5b78946f44..6dd0ff3035ed40ab47f22d76dbc22942a492dca3:/armsrc/lfops.c

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index 7ad4dabe..36efe729 100644
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -18,6 +18,7 @@
 #include "lfsampling.h"
 #include "protocols.h"
 #include "usb_cdc.h" // for usb_poll_validate_length
+#include "fpgaloader.h"
 
 /**
  * Function to do a modulation and then get samples.
@@ -876,7 +877,6 @@ void CmdHIDdemodFSK(int findone, int *high2, int *high, int *low, int ledcontrol
 	BigBuf_Clear_keep_EM();
 
 	while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
-
 		WDT_HIT();
 		if (ledcontrol) LED_A_ON();
 
@@ -887,13 +887,67 @@ void CmdHIDdemodFSK(int findone, int *high2, int *high, int *low, int ledcontrol
 		idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo, &dummyIdx);
 		
 		if (idx>0 && lo>0 && (size==96 || size==192)){
+			uint8_t bitlen = 0;
+			uint32_t fc = 0;
+			uint32_t cardnum = 0;
+			bool decoded = false;
+
 			// go over previously decoded manchester data and decode into usable tag ID
-			if (hi2 != 0){ //extra large HID tags  88/192 bits
-				Dbprintf("TAG ID: %x%08x%08x (%d)",
-				  (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-			} else {  //standard HID tags 44/96 bits
-				Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
+			if ((hi2 & 0x000FFFF) != 0){ //extra large HID tags  88/192 bits
+				uint32_t bp = hi2 & 0x000FFFFF;
+				bitlen = 63;
+				while (bp > 0) {
+					bp = bp >> 1;
+					bitlen++;
+				}
+			} else if ((hi >> 6) > 0) {
+				uint32_t bp = hi;
+				bitlen = 31;
+				while (bp > 0) {
+					bp = bp >> 1;
+					bitlen++;
+				}
+			} else if (((hi >> 5) & 1) == 0) {
+				bitlen = 37;
+			} else if ((hi & 0x0000001F) > 0 ) {
+				uint32_t bp = (hi & 0x0000001F);
+				bitlen = 31;
+				while (bp > 0) {
+					bp = bp >> 1;
+					bitlen++;
+				}
+			} else {
+				uint32_t bp = lo;
+				bitlen = 0;
+				while (bp > 0) {
+					bp = bp >> 1;
+					bitlen++;
+				}
+			}
+			switch (bitlen){
+				case 26:
+					cardnum = (lo>>1)&0xFFFF;
+					fc = (lo>>17)&0xFF;
+					decoded = true;
+					break;
+				case 35:
+					cardnum = (lo>>1)&0xFFFFF;
+					fc = ((hi&1)<<11)|(lo>>21);
+					decoded = true;
+					break;
 			}
+				
+			if (hi2 != 0) //extra large HID tags  88/192 bits
+				Dbprintf("TAG ID: %x%08x%08x (%d)",
+					(unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+			else 
+				Dbprintf("TAG ID: %x%08x (%d)",
+					(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+			
+			if (decoded)
+				Dbprintf("Format Len: %dbits - FC: %d - Card: %d",
+					(unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
+
 			if (findone){
 				if (ledcontrol)	LED_A_OFF();
 				*high2 = hi2;
@@ -1149,6 +1203,8 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 #define WRITE_0   18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
 #define WRITE_1   50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc)  432 for T55x7; 448 for E5550
 #define READ_GAP  15*8 
+// Long Leading Reference
+#define Reference_llr (136+18)*8  // Needs to be WRITR_0 + 136 clocks.
 
 void TurnReadLFOn(int delay) {
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
@@ -1166,6 +1222,265 @@ void T55xxWriteBit(int bit) {
 	WaitUS(WRITE_GAP);
 }
 
+void T55xxWrite_LLR (void)
+{
+	TurnReadLFOn (Reference_llr);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+	WaitUS(WRITE_GAP);	
+}
+
+#define START_GAPlz 31*8 
+#define WRITE_GAPlz 20*8 
+#define WRITElz_0   18*8 
+#define WRITElz_1   40*8 
+#define READ_GAP  15*8 
+
+void T55xxWriteBit_Leading0(int bit) {
+	if (!bit)
+		TurnReadLFOn(WRITElz_0);
+	else
+		TurnReadLFOn(WRITElz_1);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+	WaitUS(WRITE_GAPlz);
+//	WaitUS(160);
+}
+
+#define START_GAP1of4 31*8 // SPEC:  1*8 to 50*8 - typ 10*8 (or 15fc)
+#define WRITE_GAP1of4 20*8 // SPEC:  1*8 to 20*8 - typ 10*8 (or 10fc)
+//  00 = reference			// 8 * 8 -  - 68 * 8
+#define WRITE1of4_00  18*8 // SPEC:  8*8 to 68*8 - typ 24*8 (or 24fc)
+#define WRITE1of4_01  34*8 // SPEC: dref+9  - dref+16 - dref+24 
+#define WRITE1of4_10  50*8 // SPEC: dref+25 - dref+32 - dref+40
+#define WRITE1of4_11  66*8 // SPEC: dref+41 - dref+48 - dref+56
+#define READ1of4_GAP  15*8 
+
+void T55xxWriteBit_1of4(int bits) {
+	
+	switch (bits)
+	{
+		case 0 :  TurnReadLFOn(WRITE1of4_00); break;
+		case 1 :  TurnReadLFOn(WRITE1of4_01); break;
+		case 2 :  TurnReadLFOn(WRITE1of4_10); break;
+		case 3 :  TurnReadLFOn(WRITE1of4_11); break;
+		default:
+			TurnReadLFOn(WRITE1of4_00);
+	}		
+
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+	WaitUS(WRITE_GAP1of4);
+//	WaitUS(160);
+}
+
+void T55xxWriteBlockExt_Leading0 (uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
+
+	LED_A_ON();
+	bool PwdMode = arg & 0x1;
+	uint8_t Page = (arg & 0x2)>>1;
+	bool testMode = arg & 0x4;
+	uint32_t i = 0;
+	
+	// Set up FPGA, 125kHz
+	LFSetupFPGAForADC(95, true);
+	StartTicks();
+	// make sure tag is fully powered up...
+	WaitMS(5);
+	// Trigger T55x7 in mode.
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+
+	WaitUS(START_GAPlz);
+	
+	
+	/* 
+	   0 	: Leading Zero
+	   11   : Opcode
+	   00   : Fixed 00 if protected write (i.e. have password)
+	   <32 bit Password>
+	   0 	: Lock Bit
+	   <32 bit data> 
+	   <3 bit addr>
+
+	   	Standard Write : 0 1p L <32 data bits> <3 bit addr>
+		                 0 10 0 00000000000000000000000000000000 001
+		Protected Write: 0 1p 00 <32 pwd bits> L <32 data bits> <3 bit addr>
+					     0 10 00 00000000000000000000000000000000 0 00000000000000000000000000000000 001
+		Wake Up			 0 10 00 <32 pwd bits>
+		Protected Read   0 1p 00 <32 pwd bits> 0 <3 bit addr>
+		Standard Read    0 1p 0 <3 bit addr>
+		Page 0/1 read    0 1p
+		Reset            0 00
+		
+	*/
+		T55xxWriteBit_Leading0 (0); //T55xxWriteBit(0);
+				
+	
+		if (testMode) Dbprintf("TestMODE");
+			// Std Opcode 10
+			T55xxWriteBit_Leading0 (testMode ? 0 : 1);
+			T55xxWriteBit_Leading0 (testMode ? 1 : Page); //Page 0
+		
+	
+		if (PwdMode) {
+			// Leading zero - insert two fixed 00 between opcode and password
+			T55xxWriteBit_Leading0 (0);
+			T55xxWriteBit_Leading0 (0);
+			// Send Pwd
+			for (i = 0x80000000; i != 0; i >>= 1)
+				T55xxWriteBit_Leading0 (Pwd & i);
+		}
+	
+		// Send Lock bit
+		T55xxWriteBit_Leading0 (0);
+
+		// Send Data
+		for (i = 0x80000000; i != 0; i >>= 1)
+			T55xxWriteBit_Leading0(Data & i);
+
+		// Send Block number
+		for (i = 0x04; i != 0; i >>= 1)
+			T55xxWriteBit_Leading0 (Block & i);
+			
+		// Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
+		// so wait a little more)
+		// "there is a clock delay before programming" 
+		//  - programming takes ~5.6ms for t5577 ~18ms for E5550 or t5567
+		//  so we should wait 1 clock + 5.6ms then read response? 
+		//  but we need to know we are dealing with t5577 vs t5567 vs e5550 (or q5) marshmellow...
+		if (testMode) {
+			//TESTMODE TIMING TESTS: 
+			// <566us does nothing 
+			// 566-568 switches between wiping to 0s and doing nothing
+			// 5184 wipes and allows 1 block to be programmed.
+			// indefinite power on wipes and then programs all blocks with bitshifted data sent.
+			TurnReadLFOn(5184); 
+
+		} else {
+			TurnReadLFOn(20 * 1000);
+			//could attempt to do a read to confirm write took
+			// as the tag should repeat back the new block 
+			// until it is reset, but to confirm it we would 
+			// need to know the current block 0 config mode for
+			// modulation clock an other details to demod the response...
+			// response should be (for t55x7) a 0 bit then (ST if on) 
+			// block data written in on repeat until reset. 
+
+			//DoPartialAcquisition(20, true, 12000);
+		}
+
+		// turn field off
+		FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+		LED_A_OFF();
+	
+}
+void T55xxWriteBlockExt_1of4 (uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
+
+	LED_A_ON();
+    bool PwdMode = arg & 0x1;
+	uint8_t Page = (arg & 0x2)>>1;
+	bool testMode = arg & 0x4;
+	int bitpos;
+	uint8_t bits;
+	
+	// Set up FPGA, 125kHz
+	LFSetupFPGAForADC(95, true);
+	StartTicks();
+	// make sure tag is fully powered up...
+	WaitMS(5);
+	// Trigger T55x7 in mode.
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+
+	
+	WaitUS(START_GAP1of4);
+	
+	
+	/* 
+	   00 	: 1 if 4
+	   11   : Opcode
+	   00   : Fixed 00 if protected write (i.e. have password)
+	   <32 bit Password>
+	   0 	: Lock Bit
+	   <32 bit data> 
+	   <3 bit addr>
+
+	   	Standard Write : 00 1p L <32 data bits> <3 bit addr>
+		                 00 10 0 00000000000000000000000000000000 001
+		Protected Write: 00 1p 00 <32 pwd bits> L <32 data bits> <3 bit addr>
+					     00 10 00 00000000000000000000000000000000 0 00000000000000000000000000000000 001
+		Wake Up			 00 10 00 <32 pwd bits>
+		Protected Read   00 1p 00 <32 pwd bits> 0 <3 bit addr>
+		Standard Read    00 1p 0 <3 bit addr>
+		Page 0/1 read    00 1p
+		Reset            00 00
+		
+	*/
+		T55xxWriteBit_1of4 (0); //Send Reference 00
+	
+		if (testMode) Dbprintf("TestMODE");
+		// Std Opcode 10
+		if (testMode) bits  = 0; else bits   = 2;			// 0x or 1x
+		if (testMode) bits |= 1; else bits  += (Page);  //  x0 or x1
+		T55xxWriteBit_1of4 (bits);
+		
+		if (PwdMode) {
+			// 1 of 4 00 - insert two fixed 00 between opcode and password
+			T55xxWriteBit_1of4 (0); // 00
+			
+			// Send Pwd
+			for (bitpos = 31; bitpos >= 1; bitpos -= 2) { // 2 bits at a time
+				bits = (((Pwd >> bitpos) & 1) << 1) + ((Pwd >> (bitpos-1)) & 1);	
+				T55xxWriteBit_1of4 (bits);
+			}
+		}
+		
+		// Send Lock bit
+		bits = 0; // Add lock bit (Not Set) to the next 2 bits
+	
+		// Send Data - offset by 1 bit due to lock bit
+		// 2 bits at a time - Initilised with lock bit above
+		for (bitpos = 31; bitpos >= 1; bitpos -= 2) { 
+				bits  |= ((Data >> bitpos) & 1);  // Add Low bit
+				T55xxWriteBit_1of4 (bits);
+				bits = ((Data >> (bitpos-1)) & 1) << 1; // Set next high bit 	
+		}
+
+		// Send Block number
+		bits  |= ((Block >> 2) & 1); 
+		T55xxWriteBit_1of4 (bits);
+		bits = (Block & 3);// 1) & 2) + (Block & 1);
+		T55xxWriteBit_1of4 (bits);			
+			
+		// Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
+		// so wait a little more)
+		// "there is a clock delay before programming" 
+		//  - programming takes ~5.6ms for t5577 ~18ms for E5550 or t5567
+		//  so we should wait 1 clock + 5.6ms then read response? 
+		//  but we need to know we are dealing with t5577 vs t5567 vs e5550 (or q5) marshmellow...
+		if (testMode) {
+			//TESTMODE TIMING TESTS: 
+			// <566us does nothing 
+			// 566-568 switches between wiping to 0s and doing nothing
+			// 5184 wipes and allows 1 block to be programmed.
+			// indefinite power on wipes and then programs all blocks with bitshifted data sent.
+			TurnReadLFOn(5184); 
+
+		} else {
+			TurnReadLFOn(20 * 1000);
+			//could attempt to do a read to confirm write took
+			// as the tag should repeat back the new block 
+			// until it is reset, but to confirm it we would 
+			// need to know the current block 0 config mode for
+			// modulation clock an other details to demod the response...
+			// response should be (for t55x7) a 0 bit then (ST if on) 
+			// block data written in on repeat until reset. 
+
+			//DoPartialAcquisition(20, true, 12000);
+		}
+
+		// turn field off
+		FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+		LED_A_OFF();
+	
+}
+
 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
 void T55xxResetRead(void) {
 	LED_A_ON();
@@ -1270,12 +1585,34 @@ void T55xxWriteBlockExt(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg
 
 // Write one card block in page 0, no lock
 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
-	T55xxWriteBlockExt(Data, Block, Pwd, arg);
+//	arg 8 bit 00000000 
+//            0000000x	Password
+//            000000x0  Page
+//            00000x00  Test Mode
+//            000xx000  (0x18) where xx : 00 - Normal Write, 01 - Long Leading Reference
+//										  10 - Leading 0,    11 - 1 of 4
+	uint8_t downlink_mode;
+	
+	downlink_mode = (arg >> 3) & 0x03;
+	
+	switch (downlink_mode)
+	{
+		case 0 :	T55xxWriteBlockExt          (Data, Block, Pwd, arg);	break;
+		case 1 :    T55xxWrite_LLR ();
+					T55xxWriteBlockExt          (Data, Block, Pwd, arg);
+					break;
+		case 2 :	T55xxWriteBlockExt_Leading0 (Data, Block, Pwd, arg); 	break;
+		case 3 :	T55xxWriteBlockExt_1of4     (Data, Block, Pwd, arg); 	break;
+		
+		default:
+				T55xxWriteBlockExt    (Data, Block, Pwd, arg);
+	}					
+
 	cmd_send(CMD_ACK,0,0,0,0,0);
 }
 
 // Read one card block in page [page]
-void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
+void T55xxReadBlockExt (uint16_t arg0, uint8_t Block, uint32_t Pwd) {
 	LED_A_ON();
 	bool PwdMode = arg0 & 0x1;
 	uint8_t Page = (arg0 & 0x2) >> 1;
@@ -1325,10 +1662,163 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
 
 	// Turn the field off
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
-	cmd_send(CMD_ACK,0,0,0,0,0);    
+//	cmd_send(CMD_ACK,0,0,0,0,0);    
 	LED_A_OFF();
 }
 
+void T55xxReadBlockExt_Leading0 (uint16_t arg0, uint8_t Block, uint32_t Pwd) {
+	LED_A_ON();
+	bool     PwdMode = arg0 & 0x1;
+	uint8_t  Page    = (arg0 & 0x2) >> 1;
+	uint32_t i       = 0;
+	bool RegReadMode = (Block == 0xFF);//regular read mode
+	 
+	//clear buffer now so it does not interfere with timing later
+	BigBuf_Clear_ext(false);
+
+	//make sure block is at max 7
+	Block &= 0x7;
+
+	// Set up FPGA, 125kHz to power up the tag
+	LFSetupFPGAForADC(95, true);
+	StartTicks();
+	// make sure tag is fully powered up...
+	WaitMS(5);
+	// Trigger T55x7 Direct Access Mode with start gap
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+	WaitUS(START_GAPlz);
+
+	T55xxWriteBit_Leading0 (0); 
+
+	// Opcode 1[page]
+	T55xxWriteBit_Leading0 (1);
+	T55xxWriteBit_Leading0 (Page); //Page 0
+
+	if (PwdMode){
+		// Send Pwd
+		T55xxWriteBit_Leading0 (0);
+		T55xxWriteBit_Leading0 (0);		
+		
+		for (i = 0x80000000; i != 0; i >>= 1)
+			T55xxWriteBit_Leading0 (Pwd & i);
+	}
+	// Send a zero bit separation
+	T55xxWriteBit_Leading0(0);
+
+	// Send Block number (if direct access mode)
+	if (!RegReadMode)
+		for (i = 0x04; i != 0; i >>= 1)
+			T55xxWriteBit_Leading0(Block & i);		
+
+	// Turn field on to read the response
+	// 137*8 seems to get to the start of data pretty well... 
+	//  but we want to go past the start and let the repeating data settle in...
+	TurnReadLFOn(210*8); 
+
+	// Acquisition
+	// Now do the acquisition
+	DoPartialAcquisition(0, true, 12000, 0);
+
+	// Turn the field off
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+//	cmd_send(CMD_ACK,0,0,0,0,0);    
+	LED_A_OFF();
+}
+
+void T55xxReadBlockExt_1of4 (uint16_t arg0, uint8_t Block, uint32_t Pwd) {
+	LED_A_ON();
+	bool     PwdMode = arg0 & 0x1;
+	uint8_t  Page    = (arg0 & 0x2) >> 1;
+	//uint32_t i       = 0;
+	bool RegReadMode = (Block == 0xFF);//regular read mode
+	uint8_t bits;
+	int bitpos;
+	 
+	//clear buffer now so it does not interfere with timing later
+	BigBuf_Clear_ext(false);
+
+	//make sure block is at max 7
+	Block &= 0x7;
+
+	// Set up FPGA, 125kHz to power up the tag
+	LFSetupFPGAForADC(95, true);
+	StartTicks();
+	// make sure tag is fully powered up...
+	WaitMS(5);
+	// Trigger T55x7 Direct Access Mode with start gap
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+	WaitUS(START_GAP1of4);
+
+	T55xxWriteBit_1of4 (0); // 2 Bit 00 leading reference 
+
+	// Opcode 1[page]
+	bits = 2 + Page;
+	T55xxWriteBit_1of4 (bits);
+	
+	if (PwdMode) {
+		// 1 of 4 00 - insert two fixed 00 between opcode and password
+		T55xxWriteBit_1of4 (0); // 00
+		
+		// Send Pwd
+		for (bitpos = 31; bitpos >= 1; bitpos -= 2) { // 2 bits at a time
+			bits = (((Pwd >> bitpos) & 1) << 1) + ((Pwd >> (bitpos-1)) & 1);	
+			T55xxWriteBit_1of4 (bits);
+		}
+	}
+	
+	// Send Lock bit
+	bits = 0; // Add lock bit (Not Set) to the next 2 bits
+
+	// Send Block number (if direct access mode)
+	if (!RegReadMode){
+		// Send Block number
+		bits  += ((Block >> 2) & 1); 
+		T55xxWriteBit_1of4 (bits);
+		bits = (Block & 3); //  + (Block & 1);
+		T55xxWriteBit_1of4 (bits);				
+	}	
+
+	// Turn field on to read the response
+	// 137*8 seems to get to the start of data pretty well... 
+	//  but we want to go past the start and let the repeating data settle in...
+	TurnReadLFOn(210*8); 
+
+	// Acquisition
+	// Now do the acquisition
+	DoPartialAcquisition(0, true, 12000, 0);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+//	cmd_send(CMD_ACK,0,0,0,0,0);    
+	LED_A_OFF();
+}
+
+void T55xxReadBlock (uint16_t arg0, uint8_t Block, uint32_t Pwd) {
+//	arg0 16 bit 00000000 
+//              0000000x  Password
+//              000000x0  Page
+//              00000x00  
+//              000xx000  (0x18) where xx : 00 - Normal Write, 01 - Long Leading Reference
+//										    10 - Leading 0,    11 - 1 of 4
+	uint8_t downlink_mode;
+	
+	downlink_mode = (arg0 >> 3) & 0x03;
+
+	//  downlink mode id set to match the 2 bit as per Tech Sheet
+	switch (downlink_mode)
+	{
+		case 0 :	T55xxReadBlockExt 			(arg0, Block, Pwd); 	break;
+		case 1 :  	T55xxWrite_LLR ();
+					T55xxReadBlockExt 			(arg0, Block, Pwd);
+				    break;
+		case 2 :	T55xxReadBlockExt_Leading0 	(arg0, Block, Pwd); 	break;
+		case 3 :	T55xxReadBlockExt_1of4		(arg0, Block, Pwd);		break;
+		default:
+					T55xxReadBlockExt           (arg0, Block, Pwd) ;
+	}					
+
+//	T55xxReadBlockExt           (arg0, Block, Pwd) ;
+	cmd_send(CMD_ACK,0,0,0,0,0);
+}
+
 void T55xxWakeUp(uint32_t Pwd){
 	LED_B_ON();
 	uint32_t i = 0;
@@ -1364,8 +1854,8 @@ void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
 	}
 }
 
-// Copy HID id to card and setup block 0 config
-void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
+// Copy a HID-like card (e.g. HID Proximity, Paradox) to a T55x7 compatible card
+void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT, uint8_t preamble) {
 	uint32_t data[] = {0,0,0,0,0,0,0};
 	uint8_t last_block = 0;
 
@@ -1377,15 +1867,15 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
 		}
 		// Build the 6 data blocks for supplied 84bit ID
 		last_block = 6;
-		// load preamble (1D) & long format identifier (9E manchester encoded)
-		data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
+		// load preamble & long format identifier (9E manchester encoded)
+		data[1] = (preamble << 24) | 0x96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
 		// load raw id from hi2, hi, lo to data blocks (manchester encoded)
 		data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
 		data[3] = manchesterEncode2Bytes(hi >> 16);
 		data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
 		data[5] = manchesterEncode2Bytes(lo >> 16);
 		data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
-	}	else {
+	} else {
 		// Ensure no more than 44 bits supplied
 		if (hi>0xFFF) {
 			DbpString("Tags can only have 44 bits.");
@@ -1394,7 +1884,7 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
 		// Build the 3 data blocks for supplied 44bit ID
 		last_block = 3;
 		// load preamble
-		data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
+		data[1] = (preamble << 24) | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
 		data[2] = manchesterEncode2Bytes(lo >> 16);
 		data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
 	}
@@ -1796,7 +2286,7 @@ void Cotag(uint32_t arg0) {
 	SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
 
 	// Now set up the SSC to get the ADC samples that are now streaming at us.
-	FpgaSetupSsc();
+	FpgaSetupSsc(FPGA_MAJOR_MODE_LF_ADC);
 
 	// start clock - 1.5ticks is 1us
 	StartTicks();