X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/bf7163bdb387693ea592c212c659bbb095f84cb4..0ff9a93966032e1acb84685b5c243e7ee0d26249:/armsrc/lfops.c?ds=inline

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index fbd07e65..7d497e3c 100644
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -15,8 +15,61 @@
 #include "crc16.h"
 #include "string.h"
 
-void AcquireRawAdcSamples125k(int divisor)
+
+/**
+* Does the sample acquisition. If threshold is specified, the actual sampling 
+* is not commenced until the threshold has been reached. 
+* @param trigger_threshold - the threshold
+* @param silent - is true, now outputs are made. If false, dbprints the status
+*/
+void DoAcquisition125k_internal(int trigger_threshold,bool silent)
+{
+	uint8_t *dest = (uint8_t *)BigBuf;
+	int n = sizeof(BigBuf);
+	int i;
+
+	memset(dest, 0, n);
+	i = 0;
+	for(;;) {
+		if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
+			AT91C_BASE_SSC->SSC_THR = 0x43;
+			LED_D_ON();
+		}
+		if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
+			dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
+			LED_D_OFF();
+			if (trigger_threshold != -1 && dest[i] < trigger_threshold)
+				continue;
+			else
+				trigger_threshold = -1;
+			if (++i >= n) break;
+		}
+	}
+	if(!silent)
+	{
+		Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
+				dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
+		
+	}
+}
+/**
+* Perform sample aquisition. 
+*/
+void DoAcquisition125k(int trigger_threshold)
 {
+	DoAcquisition125k_internal(trigger_threshold, false);
+}
+
+/**
+* Setup the FPGA to listen for samples. This method downloads the FPGA bitstream 
+* if not already loaded, sets divisor and starts up the antenna. 
+* @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
+* 				   0 or 95 ==> 125 KHz
+* 				   
+**/
+void LFSetupFPGAForADC(int divisor, bool lf_field)
+{
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
 		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
 	else if (divisor == 0)
@@ -24,69 +77,55 @@ void AcquireRawAdcSamples125k(int divisor)
 	else
 		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
 
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
 
 	// Connect the A/D to the peak-detected low-frequency path.
 	SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
-
 	// Give it a bit of time for the resonant antenna to settle.
 	SpinDelay(50);
-
 	// Now set up the SSC to get the ADC samples that are now streaming at us.
 	FpgaSetupSsc();
-
+}
+/**
+* Initializes the FPGA, and acquires the samples. 
+**/
+void AcquireRawAdcSamples125k(int divisor)
+{
+	LFSetupFPGAForADC(divisor, true);
 	// Now call the acquisition routine
-	DoAcquisition125k();
+	DoAcquisition125k_internal(-1,false);
 }
+/**
+* Initializes the FPGA for snoop-mode, and acquires the samples. 
+**/
 
-// split into two routines so we can avoid timing issues after sending commands //
-void DoAcquisition125k(void)
+void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
 {
-	uint8_t *dest = (uint8_t *)BigBuf;
-	int n = sizeof(BigBuf);
-	int i;
-
-	memset(dest, 0, n);
-	i = 0;
-	for(;;) {
-		if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
-			AT91C_BASE_SSC->SSC_THR = 0x43;
-			LED_D_ON();
-		}
-		if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
-			dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
-			i++;
-			LED_D_OFF();
-			if (i >= n) break;
-		}
-	}
-	Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
-			dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
+	LFSetupFPGAForADC(divisor, false);
+	DoAcquisition125k(trigger_threshold);
 }
 
 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
 {
-	int at134khz;
 
 	/* Make sure the tag is reset */
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 	SpinDelay(2500);
 
+
+	int divisor_used = 95; // 125 KHz
 	// see if 'h' was specified
-	if (command[strlen((char *) command) - 1] == 'h')
-		at134khz = TRUE;
-	else
-		at134khz = FALSE;
 
-	if (at134khz)
-		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-	else
-		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+	if (command[strlen((char *) command) - 1] == 'h')
+		divisor_used = 88; // 134.8 KHz
 
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
 
+	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); 
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 	// Give it a bit of time for the resonant antenna to settle.
 	SpinDelay(50);
+
 	// And a little more time for the tag to fully power up
 	SpinDelay(2000);
 
@@ -98,12 +137,9 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
 		FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 		LED_D_OFF();
 		SpinDelayUs(delay_off);
-		if (at134khz)
-			FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-		else
-			FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); 
 
-		FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+		FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 		LED_D_ON();
 		if(*(command++) == '0')
 			SpinDelayUs(period_0);
@@ -113,15 +149,12 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 	LED_D_OFF();
 	SpinDelayUs(delay_off);
-	if (at134khz)
-		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-	else
-		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); 
 
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
 	// now do the read
-	DoAcquisition125k();
+	DoAcquisition125k(-1);
 }
 
 /* blank r/w tag data stream
@@ -158,6 +191,7 @@ void ReadTItag(void)
 	uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
 
 	// TI tags charge at 134.2Khz
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
 
 	// Place FPGA in passthrough mode, in this mode the CROSS_LO line
@@ -365,6 +399,7 @@ void AcquireTiType(void)
 // if not provided a valid crc will be computed from the data and written.
 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
 {
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);	
 	if(crc == 0) {
 	 	crc = update_crc16(crc, (idlo)&0xff);
 		crc = update_crc16(crc, (idlo>>8)&0xff);
@@ -436,6 +471,7 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 	int i;
 	uint8_t *tab = (uint8_t *)BigBuf;
     
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
     
 	AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
@@ -594,217 +630,243 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 		LED_A_OFF();
 }
 
-
-// loop to capture raw HID waveform then FSK demodulate the TAG ID from it
-void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
+size_t fsk_demod(uint8_t * dest, size_t size)
 {
-	uint8_t *dest = (uint8_t *)BigBuf;
-	int m=0, n=0, i=0, idx=0, found=0, lastval=0;
-  uint32_t hi2=0, hi=0, lo=0;
+	uint32_t last_transition = 0;
+	uint32_t idx = 1;
 
-	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	// we don't care about actual value, only if it's more or less than a
+	// threshold essentially we capture zero crossings for later analysis
+	uint8_t threshold_value = 127;
 
-	// Connect the A/D to the peak-detected low-frequency path.
-	SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+	// sync to first lo-hi transition, and threshold
 
-	// Give it a bit of time for the resonant antenna to settle.
-	SpinDelay(50);
+	//Need to threshold first sample
+	if(dest[0] < threshold_value) dest[0] = 0;
+	else dest[0] = 1;
 
-	// Now set up the SSC to get the ADC samples that are now streaming at us.
-	FpgaSetupSsc();
+	size_t numBits = 0;
+	// count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
+	// or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
+	// between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
+	for(idx = 1; idx < size; idx++) {
+		// threshold current value
+		if (dest[idx] < threshold_value) dest[idx] = 0;
+		else dest[idx] = 1;
 
-	for(;;) {
-		WDT_HIT();
-		if (ledcontrol)
-			LED_A_ON();
-		if(BUTTON_PRESS()) {
-			DbpString("Stopped");
-			if (ledcontrol)
-				LED_A_OFF();
-			return;
-		}
+		// Check for 0->1 transition
+		if (dest[idx-1] < dest[idx]) { // 0 -> 1 transition
 
-		i = 0;
-		m = sizeof(BigBuf);
-		memset(dest,128,m);
-		for(;;) {
-			if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
-				AT91C_BASE_SSC->SSC_THR = 0x43;
-				if (ledcontrol)
-					LED_D_ON();
-			}
-			if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
-				dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
-				// we don't care about actual value, only if it's more or less than a
-				// threshold essentially we capture zero crossings for later analysis
-				if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
-				i++;
-				if (ledcontrol)
-					LED_D_OFF();
-				if(i >= m) {
-					break;
-				}
+			if (idx-last_transition <  9) {
+					dest[numBits]=1;
+			} else {
+					dest[numBits]=0;
 			}
+			last_transition = idx;
+			numBits++;
 		}
+	}
+	return numBits; //Actually, it returns the number of bytes, but each byte represents a bit: 1 or 0
+}
 
-		// FSK demodulator
 
-		// sync to first lo-hi transition
-		for( idx=1; idx<m; idx++) {
-			if (dest[idx-1]<dest[idx])
-				lastval=idx;
-				break;
-		}
-		WDT_HIT();
+size_t aggregate_bits(uint8_t *dest,size_t size, uint8_t h2l_crossing_value,uint8_t l2h_crossing_value, uint8_t maxConsequtiveBits )
+{
+	uint8_t lastval=dest[0];
+	uint32_t idx=0;
+	size_t numBits=0;
+	uint32_t n=1;
 
-		// count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
-		// or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
-		// between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
-		for( i=0; idx<m; idx++) {
-			if (dest[idx-1]<dest[idx]) {
-				dest[i]=idx-lastval;
-				if (dest[i] <= 8) {
-						dest[i]=1;
-				} else {
-						dest[i]=0;
-				}
+	for( idx=1; idx < size; idx++) {
 
-				lastval=idx;
-				i++;
-			}
+		if (dest[idx]==lastval) {
+			n++;
+			continue;
+		}
+		//if lastval was 1, we have a 1->0 crossing
+		if ( dest[idx-1] ) {
+			n=(n+1) / h2l_crossing_value;
+		} else {// 0->1 crossing
+			n=(n+1) / l2h_crossing_value;
+		}
+		if (n == 0) n = 1;
+
+		if(n < maxConsequtiveBits)
+		{
+			memset(dest+numBits, dest[idx-1] , n);
+			numBits += n;
 		}
-		m=i;
+		n=0;
+		lastval=dest[idx];
+	}//end for
+
+	return numBits;
+
+}
+// loop to capture raw HID waveform then FSK demodulate the TAG ID from it
+void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
+{
+	uint8_t *dest = (uint8_t *)BigBuf;
+
+	size_t size=0,idx=0; //, found=0;
+	uint32_t hi2=0, hi=0, lo=0;
+
+	// Configure to go in 125Khz listen mode
+	LFSetupFPGAForADC(95, true);
+
+	while(!BUTTON_PRESS()) {
+
 		WDT_HIT();
+		if (ledcontrol) LED_A_ON();
+
+		DoAcquisition125k_internal(-1,true);
+		size  = sizeof(BigBuf);
+
+		// FSK demodulator
+		size = fsk_demod(dest, size);
 
 		// we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
-		lastval=dest[0];
-		idx=0;
-		i=0;
-		n=0;
-		for( idx=0; idx<m; idx++) {
-			if (dest[idx]==lastval) {
-				n++;
-			} else {
-				// a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,
-				// an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets
-				// swallowed up by rounding
-				// expected results are 1 or 2 bits, any more and it's an invalid manchester encoding
-				// special start of frame markers use invalid manchester states (no transitions) by using sequences
-				// like 111000
-				if (dest[idx-1]) {
-					n=(n+1)/6;			// fc/8 in sets of 6
-				} else {
-					n=(n+1)/5;			// fc/10 in sets of 5
-				}
-				switch (n) {			// stuff appropriate bits in buffer
-					case 0:
-					case 1:	// one bit
-						dest[i++]=dest[idx-1];
-						break;
-					case 2: // two bits
-						dest[i++]=dest[idx-1];
-						dest[i++]=dest[idx-1];
-						break;
-					case 3: // 3 bit start of frame markers
-						dest[i++]=dest[idx-1];
-						dest[i++]=dest[idx-1];
-						dest[i++]=dest[idx-1];
-						break;
-					// When a logic 0 is immediately followed by the start of the next transmisson
-					// (special pattern) a pattern of 4 bit duration lengths is created.
-					case 4:
-						dest[i++]=dest[idx-1];
-						dest[i++]=dest[idx-1];
-						dest[i++]=dest[idx-1];
-						dest[i++]=dest[idx-1];
-						break;
-					default:	// this shouldn't happen, don't stuff any bits
-						break;
-				}
-				n=0;
-				lastval=dest[idx];
-			}
-		}
-		m=i;
+		// 1->0 : fc/8 in sets of 6
+		// 0->1 : fc/10 in sets of 5
+		size = aggregate_bits(dest,size, 6,5,5);
+
 		WDT_HIT();
 
 		// final loop, go over previously decoded manchester data and decode into usable tag ID
 		// 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
-		for( idx=0; idx<m-6; idx++) {
+		uint8_t frame_marker_mask[] = {1,1,1,0,0,0};
+		int numshifts = 0;
+		idx = 0;
+		while( idx + sizeof(frame_marker_mask) < size) {
 			// search for a start of frame marker
-			if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
-			{
-				found=1;
-				idx+=6;
-        if (found && (hi2|hi|lo)) {
-          if (hi2 != 0){
-            Dbprintf("TAG ID: %x%08x%08x (%d)",
-                     (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-          }
-          else {
-            Dbprintf("TAG ID: %x%08x (%d)",
-                     (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-          }
-					/* if we're only looking for one tag */
-					if (findone)
-					{
-						*high = hi;
-						*low = lo;
-						return;
-					}
-          hi2=0;
-					hi=0;
-					lo=0;
-					found=0;
+			if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
+			{ // frame marker found
+				idx+=sizeof(frame_marker_mask);
+
+				while(dest[idx] != dest[idx+1] && idx < size-2)
+				{	
+					// Keep going until next frame marker (or error)
+					// Shift in a bit. Start by shifting high registers
+					hi2 = (hi2<<1)|(hi>>31);
+					hi = (hi<<1)|(lo>>31);
+					//Then, shift in a 0 or one into low
+					if (dest[idx] && !dest[idx+1])	// 1 0
+						lo=(lo<<1)|0;
+					else // 0 1
+						lo=(lo<<1)|
+								1;
+					numshifts ++;
+					idx += 2;
 				}
-			}
-			if (found) {
-				if (dest[idx] && (!dest[idx+1]) ) {
-          hi2=(hi2<<1)|(hi>>31);
-					hi=(hi<<1)|(lo>>31);
-					lo=(lo<<1)|0;
-				} else if ( (!dest[idx]) && dest[idx+1]) {
-          hi2=(hi2<<1)|(hi>>31);
-					hi=(hi<<1)|(lo>>31);
-					lo=(lo<<1)|1;
-				} else {
-					found=0;
-          hi2=0;
-					hi=0;
-					lo=0;
-				}
-				idx++;
-			}
-			if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
-			{
-				found=1;
-				idx+=6;
-				if (found && (hi|lo)) {
-          if (hi2 != 0){
-            Dbprintf("TAG ID: %x%08x%08x (%d)",
-                     (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-          }
-          else {
-            Dbprintf("TAG ID: %x%08x (%d)",
-                     (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-          }
-					/* if we're only looking for one tag */
-					if (findone)
+				//Dbprintf("Num shifts: %d ", numshifts);
+				// Hopefully, we read a tag and	 hit upon the next frame marker
+				if(idx + sizeof(frame_marker_mask) < size)
+				{
+					if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
 					{
-						*high = hi;
-						*low = lo;
-						return;
+						if (hi2 != 0){
+							Dbprintf("TAG ID: %x%08x%08x (%d)",
+								 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+						}
+						else {
+							Dbprintf("TAG ID: %x%08x (%d)",
+							 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+						}
 					}
-          hi2=0;
-					hi=0;
-					lo=0;
-					found=0;
+
 				}
+
+				// reset
+				hi2 = hi = lo = 0;
+				numshifts = 0;
+			}else
+			{
+				idx++;
 			}
 		}
 		WDT_HIT();
+
+	}
+	DbpString("Stopped");
+	if (ledcontrol) LED_A_OFF();
+}
+
+uint32_t bytebits_to_byte(uint8_t* src, int numbits)
+{
+	uint32_t num = 0;
+	for(int i = 0 ; i < numbits ; i++)
+	{
+		num = (num << 1) | (*src);
+		src++;
+	}
+	return num;
+}
+
+
+void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
+{
+	uint8_t *dest = (uint8_t *)BigBuf;
+
+	size_t size=0, idx=0;
+	uint32_t code=0, code2=0;
+
+	// Configure to go in 125Khz listen mode
+	LFSetupFPGAForADC(95, true);
+
+	while(!BUTTON_PRESS()) {
+
+
+		WDT_HIT();
+		if (ledcontrol) LED_A_ON();
+
+		DoAcquisition125k_internal(-1,true);
+		size  = sizeof(BigBuf);
+
+		// FSK demodulator
+		size = fsk_demod(dest, size);
+
+		// we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
+		// 1->0 : fc/8 in sets of 7
+		// 0->1 : fc/10 in sets of 6
+		size = aggregate_bits(dest, size, 7,6,13);
+
+		WDT_HIT();
+		
+		//Handle the data
+ 	    uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1};
+		for( idx=0; idx < size - 64; idx++) {
+
+ 	    	if ( memcmp(dest + idx, mask, sizeof(mask)) ) continue;
+
+		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx],   dest[idx+1],   dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7]);
+		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+8], dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15]);			  
+		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+16],dest[idx+17],dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23]);
+		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+24],dest[idx+25],dest[idx+26],dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31]);
+		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35],dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39]);
+		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44],dest[idx+45],dest[idx+46],dest[idx+47]);
+		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53],dest[idx+54],dest[idx+55]);
+		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
+			
+		    code = bytebits_to_byte(dest+idx,32);
+		    code2 = bytebits_to_byte(dest+idx+32,32); 
+
+		    short version = bytebits_to_byte(dest+idx+14,4); 
+		    char unknown = bytebits_to_byte(dest+idx+19,8) ;
+		    uint16_t number = bytebits_to_byte(dest+idx+36,9); 
+		    
+		    Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,unknown,number,code,code2);
+		    if (ledcontrol)	LED_D_OFF();
+		
+			// if we're only looking for one tag 
+			if (findone){
+				LED_A_OFF();
+				return;
+			}		
+		}
+		WDT_HIT();
 	}
+	DbpString("Stopped");
+	if (ledcontrol) LED_A_OFF();
 }
 
 /*------------------------------
@@ -874,8 +936,9 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 // Write one bit to card
 void T55xxWriteBit(int bit)
 {
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 	if (bit == 0)
 		SpinDelayUs(WRITE_0);
 	else
@@ -889,8 +952,9 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
 {
 	unsigned int i;
 
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
 	// Give it a bit of time for the resonant antenna to settle.
 	// And for the tag to fully power up
@@ -922,7 +986,7 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
 	// Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
 	// so wait a little more)
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 	SpinDelay(20);
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 }
@@ -933,6 +997,7 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 	uint8_t *dest = (uint8_t *)BigBuf;
 	int m=0, i=0;
   
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	m = sizeof(BigBuf);
   // Clear destination buffer before sending the command
 	memset(dest, 128, m);
@@ -943,7 +1008,7 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
   
 	LED_D_ON();
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
   
 	// Give it a bit of time for the resonant antenna to settle.
 	// And for the tag to fully power up
@@ -969,7 +1034,7 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
   
   // Turn field on to read the response
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
   
 	// Now do the acquisition
 	i = 0;
@@ -997,6 +1062,7 @@ void T55xxReadTrace(void){
 	uint8_t *dest = (uint8_t *)BigBuf;
 	int m=0, i=0;
   
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	m = sizeof(BigBuf);
   // Clear destination buffer before sending the command
 	memset(dest, 128, m);
@@ -1007,7 +1073,7 @@ void T55xxReadTrace(void){
   
 	LED_D_ON();
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
   
 	// Give it a bit of time for the resonant antenna to settle.
 	// And for the tag to fully power up
@@ -1023,7 +1089,7 @@ void T55xxReadTrace(void){
   
   // Turn field on to read the response
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
   
 	// Now do the acquisition
 	i = 0;
@@ -1166,6 +1232,26 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
 	DbpString("DONE!");
 }
 
+void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
+{
+   int data1=0, data2=0; //up to six blocks for long format
+  	
+    data1 = hi;  // load preamble
+    data2 = lo;
+    
+    LED_D_ON();
+    // Program the data blocks for supplied ID
+    // and the block 0 for HID format
+    T55xxWriteBlock(data1,1,0,0);
+    T55xxWriteBlock(data2,2,0,0);
+	
+    //Config Block
+    T55xxWriteBlock(0x00147040,0,0,0);
+    LED_D_OFF();
+	
+    DbpString("DONE!");
+}
+
 // Define 9bit header for EM410x tags
 #define EM410X_HEADER		0x1FF
 #define EM410X_ID_LENGTH	40
@@ -1370,78 +1456,81 @@ int DemodPCF7931(uint8_t **outBlocks) {
 	
 	for (bitidx = 0; i < GraphTraceLen; i++)
 	{
-    if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
-    {
-      lc = i - lastval;
-      lastval = i;
-      
-      // Switch depending on lc length:
-      // Tolerance is 1/8 of clock rate (arbitrary)
-      if (abs(lc-clock/4) < tolerance) {
-        // 16T0
-        if((i - pmc) == lc) { /* 16T0 was previous one */
-          /* It's a PMC ! */
-          i += (128+127+16+32+33+16)-1;
-          lastval = i;
-          pmc = 0;
-          block_done = 1;
-        }
-        else {
-          pmc = i;
-        }
-      } else if (abs(lc-clock/2) < tolerance) {
-        // 32TO
-        if((i - pmc) == lc) { /* 16T0 was previous one */
-          /* It's a PMC ! */
-          i += (128+127+16+32+33)-1;
-          lastval = i;
-          pmc = 0;
-          block_done = 1;
-        }
-        else if(half_switch == 1) {
-          BitStream[bitidx++] = 0;
-          half_switch = 0;
-        }
-        else
-          half_switch++;
-      } else if (abs(lc-clock) < tolerance) {
-        // 64TO
-        BitStream[bitidx++] = 1;
-      } else {
-        // Error
-        warnings++;
-        if (warnings > 10)
-        {
-          Dbprintf("Error: too many detection errors, aborting.");
-          return 0;
-        }
-      }
-      
-      if(block_done == 1) {
-        if(bitidx == 128) {
-          for(j=0; j<16; j++) {
-            Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
-            64*BitStream[j*8+6]+
-            32*BitStream[j*8+5]+
-            16*BitStream[j*8+4]+
-            8*BitStream[j*8+3]+
-            4*BitStream[j*8+2]+
-            2*BitStream[j*8+1]+
-            BitStream[j*8];
-          }
-          num_blocks++;
-        }
-        bitidx = 0;
-        block_done = 0;
-        half_switch = 0;
-      }
-      if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
-      else dir = 1;
-    }
-    if(bitidx==255)
-      bitidx=0;
-    warnings = 0;
-    if(num_blocks == 4) break;
+	    if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
+	    {
+	      lc = i - lastval;
+	      lastval = i;
+	      
+	      // Switch depending on lc length:
+	      // Tolerance is 1/8 of clock rate (arbitrary)
+	      if (abs(lc-clock/4) < tolerance) {
+	        // 16T0
+	        if((i - pmc) == lc) { /* 16T0 was previous one */
+	          /* It's a PMC ! */
+	          i += (128+127+16+32+33+16)-1;
+	          lastval = i;
+	          pmc = 0;
+	          block_done = 1;
+	        }
+	        else {
+	          pmc = i;
+	        }
+	      } else if (abs(lc-clock/2) < tolerance) {
+	        // 32TO
+	        if((i - pmc) == lc) { /* 16T0 was previous one */
+	          /* It's a PMC ! */
+	          i += (128+127+16+32+33)-1;
+	          lastval = i;
+	          pmc = 0;
+	          block_done = 1;
+	        }
+	        else if(half_switch == 1) {
+	          BitStream[bitidx++] = 0;
+	          half_switch = 0;
+	        }
+	        else
+	          half_switch++;
+	      } else if (abs(lc-clock) < tolerance) {
+	        // 64TO
+	        BitStream[bitidx++] = 1;
+	      } else {
+	        // Error
+	        warnings++;
+	        if (warnings > 10)
+	        {
+	          Dbprintf("Error: too many detection errors, aborting.");
+	          return 0;
+	        }
+	      }
+	      
+	      if(block_done == 1) {
+	        if(bitidx == 128) {
+	          for(j=0; j<16; j++) {
+	            Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
+	            64*BitStream[j*8+6]+
+	            32*BitStream[j*8+5]+
+	            16*BitStream[j*8+4]+
+	            8*BitStream[j*8+3]+
+	            4*BitStream[j*8+2]+
+	            2*BitStream[j*8+1]+
+	            BitStream[j*8];
+	          }
+	          num_blocks++;
+	        }
+	        bitidx = 0;
+	        block_done = 0;
+	        half_switch = 0;
+	      }
+	      if(i < GraphTraceLen)
+	      {
+		      if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
+		      else dir = 1;	      	
+	      }
+	    }
+	    if(bitidx==255)
+	      bitidx=0;
+	    warnings = 0;
+	    if(num_blocks == 4) break;
 	}
 	memcpy(outBlocks, Blocks, 16*num_blocks);
 	return num_blocks;
@@ -1692,8 +1781,9 @@ void SendForward(uint8_t fwd_bit_count) {
   LED_D_ON();
   
   //Field on
+  FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
   
   // Give it a bit of time for the resonant antenna to settle.
   // And for the tag to fully power up
@@ -1705,7 +1795,7 @@ void SendForward(uint8_t fwd_bit_count) {
   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
   SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
   SpinDelayUs(16*8); //16 cycles on (8us each)
   
   // now start writting
@@ -1717,7 +1807,7 @@ void SendForward(uint8_t fwd_bit_count) {
       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
       SpinDelayUs(23*8); //16-4 cycles off (8us each)
       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-      FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
+      FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
       SpinDelayUs(9*8); //16 cycles on (8us each)
     }
   }