X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/c0f15a05b36450c0182462d6d9d093c04c602b67..635d6e9befeddbf93f717a129ced376071e56881:/armsrc/lfops.c?ds=inline

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index 2e2cfd57..ab86f931 100644
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -19,56 +19,61 @@
 #include "protocols.h"
 #include "usb_cdc.h" // for usb_poll_validate_length
 
+#ifndef SHORT_COIL
+# define SHORT_COIL()	LOW(GPIO_SSC_DOUT)
+#endif
+#ifndef OPEN_COIL
+# define OPEN_COIL()	HIGH(GPIO_SSC_DOUT)
+#endif
+
 /**
  * Function to do a modulation and then get samples.
  * @param delay_off
- * @param period_0
- * @param period_1
+ * @param periods  0xFFFF0000 is period_0,  0x0000FFFF is period_1
+ * @param useHighFreg
  * @param command
  */
-void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint32_t period_1, uint8_t *command)
+void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint32_t useHighFreq, uint8_t *command)
 {
+	/* Make sure the tag is reset */
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+	SpinDelay(200);
 
-	int divisor_used = 95; // 125 KHz
-	// see if 'h' was specified
-
-	if (command[strlen((char *) command) - 1] == 'h')
-		divisor_used = 88; // 134.8 KHz
-
+	uint16_t period_0 =  periods >> 16;
+	uint16_t period_1 =  periods & 0xFFFF;
+	
+	// 95 == 125 KHz  88 == 124.8 KHz
+	int divisor_used = (useHighFreq) ? 88 : 95;
 	sample_config sc = { 0,0,1, divisor_used, 0};
 	setSamplingConfig(&sc);
+
 	//clear read buffer
 	BigBuf_Clear_keep_EM();
 
-	/* Make sure the tag is reset */
-	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelay(2500);
-
 	LFSetupFPGAForADC(sc.divisor, 1);
 
 	// And a little more time for the tag to fully power up
-	SpinDelay(2000);
+	SpinDelay(50);
 
 	// now modulate the reader field
 	while(*command != '\0' && *command != ' ') {
 		FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 		LED_D_OFF();
-		SpinDelayUs(delay_off);
+		WaitUS(delay_off);
 		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
 
 		FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 		LED_D_ON();
 		if(*(command++) == '0')
-			SpinDelayUs(period_0);
+			WaitUS(period_0);
 		else
-			SpinDelayUs(period_1);
+			WaitUS(period_1);
 	}
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 	LED_D_OFF();
-	SpinDelayUs(delay_off);
+	WaitUS(delay_off);
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
-
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
 	// now do the read
@@ -220,20 +225,20 @@ void WriteTIbyte(uint8_t b)
 	// modulate 8 bits out to the antenna
 	for (i=0; i<8; i++)
 	{
-		if (b&(1<<i)) {
-			// stop modulating antenna
+		if ( b & ( 1 << i ) ) {
+			// stop modulating antenna 1ms
 			LOW(GPIO_SSC_DOUT);
-			SpinDelayUs(1000);
-			// modulate antenna
-			HIGH(GPIO_SSC_DOUT);
-			SpinDelayUs(1000);
+			WaitUS(1000);
+			// modulate antenna 1ms
+			HIGH(GPIO_SSC_DOUT); 
+			WaitUS(1000);
 		} else {
-			// stop modulating antenna
+			// stop modulating antenna 1ms
 			LOW(GPIO_SSC_DOUT);
-			SpinDelayUs(300);
-			// modulate antenna
+			WaitUS(300);
+			// modulate antenna 1m
 			HIGH(GPIO_SSC_DOUT);
-			SpinDelayUs(1700);
+			WaitUS(1700);
 		}
 	}
 }
@@ -270,7 +275,7 @@ void AcquireTiType(void)
 	AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
 	AT91C_BASE_SSC->SSC_TCMR = 0;
 	AT91C_BASE_SSC->SSC_TFMR = 0;
-
+	// iceman, FpgaSetupSsc() ?? the code above? can it be replaced?
 	LED_D_ON();
 
 	// modulate antenna
@@ -380,36 +385,35 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
 	AcquireTiType();
 
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	DbpString("Now use 'lf ti read' to check");
+	DbpString("Now use `lf ti read` to check");
 }
 
 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 {
-	int i;
+	int i = 0;
 	uint8_t *tab = BigBuf_get_addr();
 
-	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
 
 	AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
 	AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
 	AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
 
- #define SHORT_COIL()	LOW(GPIO_SSC_DOUT)
- #define OPEN_COIL()	HIGH(GPIO_SSC_DOUT)
-
-	i = 0;
 	for(;;) {
+		WDT_HIT();
+
+		if (ledcontrol) LED_D_ON();
+				
 		//wait until SSC_CLK goes HIGH
 		while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
-			if(BUTTON_PRESS() || usb_poll_validate_length() ) {
-				DbpString("Stopped");
-				return;
-			}
 			WDT_HIT();
+			if ( usb_poll_validate_length() || BUTTON_PRESS() ) {
+				FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+				LED_D_OFF();
+				return;				
+			}
 		}
-		if (ledcontrol) LED_D_ON();
-
+		
 		if(tab[i])
 			OPEN_COIL();
 		else
@@ -419,20 +423,21 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 		
 		//wait until SSC_CLK goes LOW
 		while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
-			if( BUTTON_PRESS() || usb_poll_validate_length() ) {
-				DbpString("Stopped");
-				return;
-			}
 			WDT_HIT();
+			if ( usb_poll_validate_length() || BUTTON_PRESS() ) {
+				FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+				LED_D_OFF();
+				return;				
+			}
 		}
 
 		i++;
 		if(i == period) {
-
 			i = 0;
 			if (gap) {
+				WDT_HIT();
 				SHORT_COIL();
-				SpinDelayUs(gap);
+				WaitUS(gap);
 			}
 		}
 	}
@@ -526,7 +531,10 @@ static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
 // simulate a HID tag until the button is pressed
 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 {
-	int n=0, i=0;
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+	set_tracing(FALSE);
+		
+	int n = 0, i = 0;
 	/*
 	 HID tag bitstream format
 	 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
@@ -537,7 +545,7 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 	 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
 	*/
 
-	if (hi>0xFFF) {
+	if (hi > 0xFFF) {
 		DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
 		return;
 	}
@@ -569,7 +577,8 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 			fc(8,  &n); fc(10, &n);		// high-low transition
 		}
 	}
-
+	WDT_HIT();
+	
 	if (ledcontrol)	LED_A_ON();
 	SimulateTagLowFrequency(n, 0, ledcontrol);
 	if (ledcontrol)	LED_A_OFF();
@@ -580,8 +589,14 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
 {
-	int ledcontrol=1;
-	int n=0, i=0;
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+
+	// free eventually allocated BigBuf memory
+	BigBuf_free(); BigBuf_Clear_ext(false);
+	clear_trace();
+	set_tracing(FALSE);
+	
+	int ledcontrol = 1, n = 0, i = 0;
 	uint8_t fcHigh = arg1 >> 8;
 	uint8_t fcLow = arg1 & 0xFF;
 	uint16_t modCnt = 0;
@@ -589,13 +604,15 @@ void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
 	uint8_t invert = (arg2 >> 8) & 1;
 
 	for (i=0; i<size; i++){
-		if (BitStream[i] == invert){
+		
+		if (BitStream[i] == invert)
 			fcAll(fcLow, &n, clk, &modCnt);
-		} else {
+		else
 			fcAll(fcHigh, &n, clk, &modCnt);
-		}
 	}
-	Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
+	WDT_HIT();
+	
+	Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d", fcHigh, fcLow, clk, invert, n);
 
 	if (ledcontrol)	LED_A_ON();
 	SimulateTagLowFrequency(n, 0, ledcontrol);
@@ -628,25 +645,39 @@ static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
 		memset(dest+(*n), c ^ *phase, clock);
 		*phase ^= 1;
 	}
+	*n += clock;
+}
 
+static void stAskSimBit(int *n, uint8_t clock) {
+	uint8_t *dest = BigBuf_get_addr();
+	uint8_t halfClk = clock/2;
+	//ST = .5 high .5 low 1.5 high .5 low 1 high	
+	memset(dest+(*n), 1, halfClk);
+	memset(dest+(*n) + halfClk, 0, halfClk);
+	memset(dest+(*n) + clock, 1, clock + halfClk);
+	memset(dest+(*n) + clock*2 + halfClk, 0, halfClk);
+	memset(dest+(*n) + clock*3, 1, clock);
+	*n += clock*4;
 }
 
 // args clock, ask/man or askraw, invert, transmission separator
 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
 {
-	int ledcontrol = 1;
-	int n=0, i=0;
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);	
+	set_tracing(FALSE);
+	
+	int ledcontrol = 1, n = 0, i = 0;
 	uint8_t clk = (arg1 >> 8) & 0xFF;
 	uint8_t encoding = arg1 & 0xFF;
 	uint8_t separator = arg2 & 1;
 	uint8_t invert = (arg2 >> 8) & 1;
 
-	if (encoding==2){  //biphase
-		uint8_t phase=0;
+	if (encoding == 2){  //biphase
+		uint8_t phase = 0;
 		for (i=0; i<size; i++){
 			biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
 		}
-		if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
+		if (phase == 1) { //run a second set inverted to keep phase in check
 			for (i=0; i<size; i++){
 				biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
 			}
@@ -661,9 +692,13 @@ void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
 			}
 		}
 	}
-	
-	if (separator==1) Dbprintf("sorry but separator option not yet available"); 
+	if (separator==1 && encoding == 1)
+		stAskSimBit(&n, clk);
+	else if (separator==1)
+		Dbprintf("sorry but separator option not yet available");
 
+	WDT_HIT();
+	
 	Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
 
 	if (ledcontrol)	LED_A_ON();
@@ -697,8 +732,10 @@ static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, b
 // args clock, carrier, invert,
 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
 {
-	int ledcontrol = 1;
-	int n=0, i=0;
+	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);	
+	set_tracing(FALSE);
+	
+	int ledcontrol = 1, n = 0, i = 0;
 	uint8_t clk = arg1 >> 8;
 	uint8_t carrier = arg1 & 0xFF;
 	uint8_t invert = arg2 & 0xFF;
@@ -710,6 +747,9 @@ void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
 			pskSimBit(carrier, &n, clk, &curPhase, TRUE);
 		}
 	}
+	
+	WDT_HIT();
+	
 	Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
 		   
 	if (ledcontrol)	LED_A_ON();
@@ -856,7 +896,6 @@ void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 
 	        size = removeParity(dest, idx+8, 4, 1, 88);
 		if (size != 66) continue;
-	        // ok valid card found!
 
 	        // Index map
 	        // 0           10         20        30          40        50        60
@@ -866,37 +905,51 @@ void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 	        // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
 	        // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 	        // |26 bit|   |-117--| |-----142------|
+			//
+			// 00110010 0 0000011111010000000000000001000100101000100001111 0 00000000 
+			// bbbbbbbb w ffffffffffffffffccccccccccccccccccccccccccccccccc w xxxxxxxx
+			// |50 bit|   |----4000------||-----------2248975-------------| 			
+			//
 	        // b = format bit len, o = odd parity of last 3 bits
 	        // f = facility code, c = card number
 	        // w = wiegand parity
-	        // (26 bit format shown)
 
 	        uint32_t fc = 0;
 	        uint32_t cardnum = 0;
 	        uint32_t code1 = 0;
 	        uint32_t code2 = 0;
 	        uint8_t fmtLen = bytebits_to_byte(dest,8);
-	        if (fmtLen==26){
-	                fc = bytebits_to_byte(dest+9, 8);
-	                cardnum = bytebits_to_byte(dest+17, 16);
-	                code1 = bytebits_to_byte(dest+8,fmtLen);
-	                Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %d - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
-	        } else {
-	                cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
-	                if (fmtLen>32){
-                        code1 = bytebits_to_byte(dest+8,fmtLen-32);
-                        code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
-                        Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
-                } else{
-                        code1 = bytebits_to_byte(dest+8,fmtLen);
-                        Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
-                }
+			switch(fmtLen) {
+				case 26: 
+					fc = bytebits_to_byte(dest + 9, 8);
+					cardnum = bytebits_to_byte(dest + 17, 16);
+					code1 = bytebits_to_byte(dest + 8,fmtLen);
+					Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
+					break;
+				case 50:
+					fc = bytebits_to_byte(dest + 9, 16);
+					cardnum = bytebits_to_byte(dest + 25, 32);
+					code1 = bytebits_to_byte(dest + 8, (fmtLen-32) );
+					code2 = bytebits_to_byte(dest + 8 + (fmtLen-32), 32);
+					Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, code2, rawHi2, rawHi, rawLo);
+					break;
+				default:
+					if (fmtLen > 32 ) {
+						cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
+						code1 = bytebits_to_byte(dest+8,fmtLen-32);
+						code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
+						Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
+					} else {
+						cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
+						code1 = bytebits_to_byte(dest+8,fmtLen);
+						Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
+					}
+					break;		
 			}
 			if (findone){
 				if (ledcontrol)	LED_A_OFF();
 				return;
 			}
-			// reset
 		idx = 0;
 		WDT_HIT();
 	}
@@ -979,7 +1032,7 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 	//clear read buffer
 	BigBuf_Clear_keep_EM();
 	
-// Configure to go in 125Khz listen mode
+	// Configure to go in 125Khz listen mode
 	LFSetupFPGAForADC(95, true);
 
 	while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
@@ -1063,7 +1116,7 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
  * Q5 tags seems to have issues when these values changes. 
  */
 
-#define START_GAP 31*8 // was 250 // SPEC:  1*8 to 50*8 - typ 15*8 (or 15fc)
+#define START_GAP 50*8 // was 250 // SPEC:  1*8 to 50*8 - typ 15*8 (or 15fc)
 #define WRITE_GAP 20*8 // was 160 // SPEC:  1*8 to 20*8 - typ 10*8 (or 10fc)
 #define WRITE_0   18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
 #define WRITE_1   50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc)  432 for T55x7; 448 for E5550
@@ -1085,13 +1138,12 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 
 void TurnReadLFOn(int delay) {
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
-	// Give it a bit of time for the resonant antenna to settle.
 
 	// measure antenna strength.
 	//int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
-	// where to save it
-	
-	SpinDelayUs(delay);
+
+	// Give it a bit of time for the resonant antenna to settle.
+	WaitUS(delay);
 }
 
 // Write one bit to card
@@ -1101,7 +1153,7 @@ void T55xxWriteBit(int bit) {
 	else
 		TurnReadLFOn(WRITE_1);
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelayUs(WRITE_GAP);
+	WaitUS(WRITE_GAP);
 }
 
 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
@@ -1115,7 +1167,7 @@ void T55xxResetRead(void) {
 
 	// Trigger T55x7 in mode.
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelayUs(START_GAP);
+	WaitUS(START_GAP);
 
 	// reset tag - op code 00
 	T55xxWriteBit(0);
@@ -1145,7 +1197,7 @@ void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg)
 	
 	// Trigger T55x7 in mode.
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelayUs(START_GAP);
+	WaitUS(START_GAP);
 
 	// Opcode 10
 	T55xxWriteBit(1);
@@ -1194,17 +1246,18 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
 	bool RegReadMode = (Block == 0xFF);
 	
 	//clear buffer now so it does not interfere with timing later
-	BigBuf_Clear_ext(false);
+	BigBuf_Clear_keep_EM();
 
 	//make sure block is at max 7
 	Block &= 0x7;
 
 	// Set up FPGA, 125kHz to power up the tag
 	LFSetupFPGAForADC(95, true);
+	SpinDelay(3);
 	
 	// Trigger T55x7 Direct Access Mode with start gap
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelayUs(START_GAP);
+	WaitUS(START_GAP);
 	
 	// Opcode 1[page]
 	T55xxWriteBit(1);
@@ -1220,8 +1273,8 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
 	
 	// Send Block number (if direct access mode)
 	if (!RegReadMode)
-	for (i = 0x04; i != 0; i >>= 1)
-		T55xxWriteBit(Block & i);
+		for (i = 0x04; i != 0; i >>= 1)
+			T55xxWriteBit(Block & i);
 
 	// Turn field on to read the response
 	TurnReadLFOn(READ_GAP);
@@ -1244,7 +1297,7 @@ void T55xxWakeUp(uint32_t Pwd){
 	
 	// Trigger T55x7 Direct Access Mode
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelayUs(START_GAP);
+	WaitUS(START_GAP);
 	
 	// Opcode 10
 	T55xxWriteBit(1);
@@ -1259,7 +1312,6 @@ void T55xxWakeUp(uint32_t Pwd){
 }
 
 /*-------------- Cloning routines -----------*/
-
 void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
 	// write last block first and config block last (if included)
 	for (uint8_t i = numblocks+startblock; i > startblock; i--)
@@ -1319,15 +1371,14 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
 void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
 	uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
 	//TODO add selection of chip for Q5 or T55x7
-	// data[0] = (((64-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
+	//t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
+	// data[0] = (64 << T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
 
 	LED_D_ON();
 	// Program the data blocks for supplied ID
 	// and the block 0 config
 	WriteT55xx(data, 0, 3);
-
 	LED_D_OFF();
-
 	DbpString("DONE!");
 }
 
@@ -1361,6 +1412,7 @@ void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t
 // clone viking tag to T55xx
 void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
 	uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
+	//t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
 	if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
 	// Program the data blocks for supplied ID and the block 0 config
 	WriteT55xx(data, 0, 3);
@@ -1432,7 +1484,7 @@ void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
 	LED_D_ON();
 
 	// Write EM410x ID
-	uint32_t data[] = {0, (uint32_t)(id>>32), id & 0xFFFFFFFF};
+	uint32_t data[] = {0, (uint32_t)(id>>32), (uint32_t)(id & 0xFFFFFFFF)};
 
 	clock = (card & 0xFF00) >> 8;
 	clock = (clock == 0) ? 64 : clock;
@@ -1448,7 +1500,7 @@ void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
 		clock = (clock-2)>>1;  //n = (RF-2)/2
 		data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
 	}
-
+ 
 	WriteT55xx(data, 0, 3);
 
 	LED_D_OFF();
@@ -1576,20 +1628,20 @@ void SendForward(uint8_t fwd_bit_count) {
 	fwd_bit_sz--; //prepare next bit modulation
 	fwd_write_ptr++;
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
-	SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
+	WaitUS(55*8); //55 cycles off (8us each)for 4305	// ICEMAN:  problem with (us) clock is  21.3us increments
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
-	SpinDelayUs(16*8); //16 cycles on (8us each)
+	WaitUS(16*8); //16 cycles on (8us each)	// ICEMAN:  problem with (us) clock is  21.3us increments
 
 	// now start writting
 	while(fwd_bit_sz-- > 0) { //prepare next bit modulation
 		if(((*fwd_write_ptr++) & 1) == 1)
-			SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
+			WaitUS(32*8); //32 cycles at 125Khz (8us each)	// ICEMAN:  problem with (us) clock is  21.3us increments
 		else {
 			//These timings work for 4469/4269/4305 (with the 55*8 above)
 			FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
-			SpinDelayUs(23*8); //16-4 cycles off (8us each)
+			WaitUS(23*8); //16-4 cycles off (8us each)	// ICEMAN:  problem with (us) clock is  21.3us increments
 			FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
-			SpinDelayUs(9*8); //16 cycles on (8us each)
+			WaitUS(9*8); //16 cycles on (8us each)	// ICEMAN:  problem with (us) clock is  21.3us increments
 		}
 	}
 }