X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/e30c654b196a87a13ae7f7d4ced930b296c038ec..a1f3bb120f103c89dbc160d25b31d811e425d29e:/armsrc/util.c?ds=sidebyside diff --git a/armsrc/util.c b/armsrc/util.c index ae2e7247..6d34ae5e 100644 --- a/armsrc/util.c +++ b/armsrc/util.c @@ -1,78 +1,40 @@ //----------------------------------------------------------------------------- -// Utility functions used in many places, not specific to any piece of code. // Jonathan Westhues, Sept 2005 +// +// This code is licensed to you under the terms of the GNU GPL, version 2 or, +// at your option, any later version. See the LICENSE.txt file for the text of +// the license. +//----------------------------------------------------------------------------- +// Utility functions used in many places, not specific to any piece of code. //----------------------------------------------------------------------------- + #include "proxmark3.h" +#include "util.h" +#include "string.h" #include "apps.h" -void *memcpy(void *dest, const void *src, int len) -{ - BYTE *d = dest; - const BYTE *s = src; - while((len--) > 0) { - *d = *s; - d++; - s++; - } - return dest; +size_t nbytes(size_t nbits) { + return (nbits/8)+((nbits%8)>0); } -void *memset(void *dest, int c, int len) -{ - BYTE *d = dest; - while((len--) > 0) { - *d = c; - d++; +uint32_t SwapBits(uint32_t value, int nrbits) { + int i; + uint32_t newvalue = 0; + for(i = 0; i < nrbits; i++) { + newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i); } - return dest; + return newvalue; } -int memcmp(const void *av, const void *bv, int len) -{ - const BYTE *a = av; - const BYTE *b = bv; - - while((len--) > 0) { - if(*a != *b) { - return *a - *b; - } - a++; - b++; - } - return 0; -} - -int strlen(char *str) -{ - int l = 0; - while(*str) { - l++; - str++; - } - return l; -} - -char* strncat(char *dest, const char *src, unsigned int n) -{ - unsigned int dest_len = strlen(dest); - unsigned int i; - - for (i = 0 ; i < n && src[i] != '\0' ; i++) - dest[dest_len + i] = src[i]; - dest[dest_len + i] = '\0'; - - return dest; -} - -void num_to_bytes(uint64_t n, size_t len, byte_t* dest) +void num_to_bytes(uint64_t n, size_t len, uint8_t* dest) { while (len--) { - dest[len] = (byte_t) n; + dest[len] = (uint8_t) n; n >>= 8; } } -uint64_t bytes_to_num(byte_t* src, size_t len) +uint64_t bytes_to_num(uint8_t* src, size_t len) { uint64_t num = 0; while (len--) @@ -139,12 +101,12 @@ int BUTTON_CLICKED(int ms) AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0; AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff; - WORD start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; + uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; int letoff = 0; for(;;) { - WORD now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; + uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; // We haven't let off the button yet if (!letoff) @@ -162,7 +124,7 @@ int BUTTON_CLICKED(int ms) // Still haven't let it off else // Have we held down a full second? - if (now == (WORD)(start + ticks)) + if (now == (uint16_t)(start + ticks)) return BUTTON_HOLD; } @@ -174,7 +136,7 @@ int BUTTON_CLICKED(int ms) // Have we ran out of time to double click? else - if (now == (WORD)(start + ticks)) + if (now == (uint16_t)(start + ticks)) // At least we did a single click return BUTTON_SINGLE_CLICK; @@ -202,11 +164,11 @@ int BUTTON_HELD(int ms) AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0; AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff; - WORD start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; + uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; for(;;) { - WORD now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; + uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; // As soon as our button let go, we didn't hold long enough if (!BUTTON_PRESS()) @@ -214,7 +176,7 @@ int BUTTON_HELD(int ms) // Have we waited the full second? else - if (now == (WORD)(start + ticks)) + if (now == (uint16_t)(start + ticks)) return BUTTON_HOLD; WDT_HIT(); @@ -237,11 +199,11 @@ void SpinDelayUs(int us) AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0; AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff; - WORD start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; + uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; for(;;) { - WORD now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; - if (now == (WORD)(start + ticks)) + uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; + if (now == (uint16_t)(start + ticks)) return; WDT_HIT(); @@ -287,3 +249,145 @@ void FormatVersionInformation(char *dst, int len, const char *prefix, void *vers strncat(dst, " ", len); strncat(dst, v->buildtime, len); } + +// ------------------------------------------------------------------------- +// timer lib +// ------------------------------------------------------------------------- +// test procedure: +// +// ti = GetTickCount(); +// SpinDelay(1000); +// ti = GetTickCount() - ti; +// Dbprintf("timer(1s): %d t=%d", ti, GetTickCount()); + +void StartTickCount() +{ +// must be 0x40, but on my cpu - included divider is optimal +// 0x20 - 1 ms / bit +// 0x40 - 2 ms / bit + + AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST + 0x001D; // was 0x003B +} + +/* +* Get the current count. +*/ +uint32_t RAMFUNC GetTickCount(){ + return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2; +} + +// ------------------------------------------------------------------------- +// microseconds timer +// ------------------------------------------------------------------------- +void StartCountUS() +{ + AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14); +// AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0; + AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE; + + // fast clock + AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable + AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks + AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR | + AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET; + AT91C_BASE_TC0->TC_RA = 1; + AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000 + + AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable + AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0 + + AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; + AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; + AT91C_BASE_TCB->TCB_BCR = 1; + } + +uint32_t RAMFUNC GetCountUS(){ + return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10); +} + +static uint32_t GlobalUsCounter = 0; + +uint32_t RAMFUNC GetDeltaCountUS(){ + uint32_t g_cnt = GetCountUS(); + uint32_t g_res = g_cnt - GlobalUsCounter; + GlobalUsCounter = g_cnt; + return g_res; +} + + +// ------------------------------------------------------------------------- +// Timer for iso14443 commands. Uses ssp_clk from FPGA +// ------------------------------------------------------------------------- +void StartCountSspClk() +{ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2); // Enable Clock to all timers + AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 // XC0 Clock = TIOA1 + | AT91C_TCB_TC1XC1S_NONE // XC1 Clock = none + | AT91C_TCB_TC2XC2S_TIOA0; // XC2 Clock = TIOA0 + + // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs: + AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // disable TC1 + AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz + | AT91C_TC_CPCSTOP // Stop clock on RC compare + | AT91C_TC_EEVTEDG_RISING // Trigger on rising edge of Event + | AT91C_TC_EEVT_TIOB // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16) + | AT91C_TC_ENETRG // Enable external trigger event + | AT91C_TC_WAVESEL_UP // Upmode without automatic trigger on RC compare + | AT91C_TC_WAVE // Waveform Mode + | AT91C_TC_AEEVT_SET // Set TIOA1 on external event + | AT91C_TC_ACPC_CLEAR; // Clear TIOA1 on RC Compare + AT91C_BASE_TC1->TC_RC = 0x04; // RC Compare value = 0x04 + + // use TC0 to count TIOA1 pulses + AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // disable TC0 + AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0 // TC0 clock = XC0 clock = TIOA1 + | AT91C_TC_WAVE // Waveform Mode + | AT91C_TC_WAVESEL_UP // just count + | AT91C_TC_ACPA_CLEAR // Clear TIOA0 on RA Compare + | AT91C_TC_ACPC_SET; // Set TIOA0 on RC Compare + AT91C_BASE_TC0->TC_RA = 1; // RA Compare value = 1; pulse width to TC2 + AT91C_BASE_TC0->TC_RC = 0; // RC Compare value = 0; increment TC2 on overflow + + // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk) + AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; // disable TC2 + AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2 // TC2 clock = XC2 clock = TIOA0 + | AT91C_TC_WAVE // Waveform Mode + | AT91C_TC_WAVESEL_UP; // just count + + AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; // enable TC0 + AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; // enable TC1 + AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN; // enable TC2 + + // + // synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14446 mode, otherwise the frame signal would not be present + // + while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); // wait for ssp_frame to go high (start of frame) + while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); // wait for ssp_frame to be low + // after the falling edge of ssp_frame, there is delay of 1/13,56MHz (73ns) until the next rising edge of ssp_clk. This are only a few + // processor cycles. We therefore may or may not be able to sync on this edge. Therefore better make sure that we miss it: + while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high + // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame + // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge + AT91C_BASE_TCB->TCB_BCR = 1; // assert Sync (set all timers to 0 on next active clock edge) + // at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0) + // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on, + // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer. + // (just started with the transfer of the 4th Bit). + // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before + // we can use the counter. + while (AT91C_BASE_TC0->TC_CV < 0xFFF0); +} + + +uint32_t RAMFUNC GetCountSspClk(){ + uint32_t tmp_count; + tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV; + if ((tmp_count & 0x0000ffff) == 0) { //small chance that we may have missed an increment in TC2 + return (AT91C_BASE_TC2->TC_CV << 16); + } + else { + return tmp_count; + } +} + +