X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/e4a8d1e2acc29213bcc204271ec85eb43bcf0716..f4d7d1fed17809ea9d7b919bd32265d2b6cc895f:/armsrc/legicrf.c diff --git a/armsrc/legicrf.c b/armsrc/legicrf.c index ff193edb..f58cb442 100644 --- a/armsrc/legicrf.c +++ b/armsrc/legicrf.c @@ -69,7 +69,7 @@ static void setup_timer(void) { */ // At TIMER_CLOCK3 (MCK/32) -// testing calculating in (us) microseconds. +// testing calculating in ticks. 1.5ticks = 1us #define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks #define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks #define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */ @@ -92,11 +92,7 @@ static void setup_timer(void) { # define OPEN_COIL HIGH(GPIO_SSC_DOUT); #endif #ifndef LINE_IN -# define LINE_IN \ - do { \ - AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN; \ - AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN; \ - } while (0); +# define LINE_IN AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN; #endif // Pause pulse, off in 20us / 30ticks, // ONE / ZERO bit pulse, @@ -184,7 +180,7 @@ void frame_send_tag(uint16_t response, uint8_t bits) { AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; /* TAG_FRAME_WAIT -> shift by 2 */ - legic_prng_forward(2); + legic_prng_forward(3); response ^= legic_prng_get_bits(bits); /* Wait for the frame start */ @@ -205,8 +201,7 @@ void frame_send_tag(uint16_t response, uint8_t bits) { */ void frame_sendAsReader(uint32_t data, uint8_t bits){ - uint32_t starttime = GET_TICKS, send = 0; - uint16_t mask = 1; + uint32_t starttime = GET_TICKS, send = 0, mask = 1; // xor lsfr onto data. send = data ^ legic_prng_get_bits(bits); @@ -222,7 +217,7 @@ void frame_sendAsReader(uint32_t data, uint8_t bits){ COIL_PULSE(0); // log - uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1), BYTEx(send, 0), BYTEx(send, 1)}; + uint8_t cmdbytes[] = {bits, BYTEx(data,0), BYTEx(data,1), BYTEx(data,2), BYTEx(send,0), BYTEx(send,1), BYTEx(send,2)}; LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, TRUE); } @@ -258,9 +253,6 @@ static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) { frame_clean(f); - /* Bitbang the receiver */ - LINE_IN; - // calibrate the prng. legic_prng_forward(2); data = legic_prng_get_bits(bits); @@ -305,19 +297,18 @@ static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) { // Setup pm3 as a Legic Reader static uint32_t setup_phase_reader(uint8_t iv) { - // Switch on carrier and let the tag charge for 1ms + // Switch on carrier and let the tag charge for 5ms HIGH(GPIO_SSC_DOUT); - WaitUS(5000); + WaitUS(5000); ResetTicks(); - // no keystream yet legic_prng_init(0); // send IV handshake frame_sendAsReader(iv, 7); - // Now both tag and reader has same IV. Prng can start. + // tag and reader has same IV. legic_prng_init(iv); frame_receiveAsReader(¤t_frame, 6); @@ -341,20 +332,22 @@ static uint32_t setup_phase_reader(uint8_t iv) { return current_frame.data; } -static void LegicCommonInit(void) { +void LegicCommonInit(bool clear_mem) { FpgaDownloadAndGo(FPGA_BITSTREAM_HF); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX); SetAdcMuxFor(GPIO_MUXSEL_HIPKD); /* Bitbang the transmitter */ - LOW(GPIO_SSC_DOUT); + SHORT_COIL; AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; - + AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN; + // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier. cardmem = BigBuf_get_EM_addr(); - memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE); + if ( clear_mem ) + memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE); clear_trace(); set_tracing(TRUE); @@ -365,7 +358,7 @@ static void LegicCommonInit(void) { // Switch off carrier, make sure tag is reset static void switch_off_tag_rwd(void) { - LOW(GPIO_SSC_DOUT); + SHORT_COIL; WaitUS(20); WDT_HIT(); } @@ -396,7 +389,7 @@ int legic_read_byte( uint16_t index, uint8_t cmd_sz) { calcCrc = legic4Crc(LEGIC_READ, index, byte, cmd_sz); if( calcCrc != crc ) { - Dbprintf("!!! crc mismatch: expected %x but got %x !!!", calcCrc, crc); + Dbprintf("!!! crc mismatch: %x != %x !!!", calcCrc, crc); return -1; } @@ -409,64 +402,66 @@ int legic_read_byte( uint16_t index, uint8_t cmd_sz) { * - wait until the tag sends back an ACK ('1' bit unencrypted) * - forward the prng based on the timing */ -int legic_write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz) { - - // crc - crc_clear(&legic_crc); - crc_update(&legic_crc, 0, 1); /* CMD_WRITE */ - crc_update(&legic_crc, index, addr_sz); - crc_update(&legic_crc, byte, 8); - uint32_t crc = crc_finish(&legic_crc); - uint32_t crc2 = legic4Crc(LEGIC_WRITE, index, byte, addr_sz+1); - if ( crc != crc2 ) { - Dbprintf("crc is missmatch"); - return 1; - } +bool legic_write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz) { + + bool isOK = false; + int8_t i = 40; + uint8_t edges = 0; + uint8_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd; + uint32_t steps = 0, next_bit_at, start, crc, old_level = 0; + + crc = legic4Crc(LEGIC_WRITE, index, byte, addr_sz+1); + // send write command - uint32_t cmd = ((crc <<(addr_sz+1+8)) //CRC - |(byte <<(addr_sz+1)) //Data - |(index <<1) //index - | LEGIC_WRITE); //CMD = Write - - uint32_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd - - legic_prng_forward(2); + uint32_t cmd = LEGIC_WRITE; + cmd |= index << 1; // index + cmd |= byte << (addr_sz+1); // Data + cmd |= (crc & 0xF ) << (addr_sz+1+8); // CRC - WaitTicks(330); + WaitTicks(240); frame_sendAsReader(cmd, cmd_sz); - - /* Bitbang the receiver */ + LINE_IN; - int t, old_level = 0, edges = 0; - int next_bit_at = 0; - - // ACK 3.6ms = 3600us * 1.5 = 5400ticks. - WaitTicks(5360); + start = GET_TICKS; - for( t = 0; t < 80; ++t) { + // ACK, - one single "1" bit after 3.6ms + // 3.6ms = 3600us * 1.5 = 5400ticks. + WaitTicks(5400); + + next_bit_at = GET_TICKS + TAG_BIT_PERIOD; + + while ( i-- ) { + WDT_HIT(); edges = 0; - next_bit_at += TAG_BIT_PERIOD; - while(timer->TC_CV < next_bit_at) { + while ( GET_TICKS < next_bit_at) { + volatile uint32_t level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN); - if(level != old_level) - edges++; + + if (level != old_level) + ++edges; old_level = level; } - /* expected are 42 edges (ONE) */ + + next_bit_at += TAG_BIT_PERIOD; + + // We expect 42 edges (ONE) if(edges > 20 ) { - int t = timer->TC_CV; - int c = t / TAG_BIT_PERIOD; - - ResetTimer(timer); - legic_prng_forward(c); - return 0; + steps = ( (GET_TICKS - start) / TAG_BIT_PERIOD); + legic_prng_forward(steps); + isOK = true; + goto OUT; } } - - return -1; + +OUT: ; + legic_prng_forward(1); + + uint8_t cmdbytes[] = {1, isOK, BYTEx(steps, 0), BYTEx(steps, 1) }; + LogTrace(cmdbytes, sizeof(cmdbytes), start, GET_TICKS, NULL, FALSE); + return isOK; } int LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) { @@ -475,20 +470,16 @@ int LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) { uint8_t isOK = 1; legic_card_select_t card; - LegicCommonInit(); + LegicCommonInit(TRUE); if ( legic_select_card_iv(&card, iv) ) { isOK = 0; goto OUT; } - switch_off_tag_rwd(); - - if (len + offset >= card.cardsize) + if (len + offset > card.cardsize) len = card.cardsize - offset; - setup_phase_reader(iv); - LED_B_ON(); while (i < len) { int r = legic_read_byte(offset + i, card.cmdsize); @@ -512,61 +503,39 @@ OUT: void LegicRfWriter(uint16_t offset, uint16_t len, uint8_t iv, uint8_t *data) { - uint8_t isOK = 1; + #define LOWERLIMIT 4 + uint8_t isOK = 1, msg = 0; + legic_card_select_t card; - // UID not is writeable. - if ( offset <= 4 ) { + // uid NOT is writeable. + if ( offset <= LOWERLIMIT ) { isOK = 0; goto OUT; } - legic_card_select_t card; - - LegicCommonInit(); + LegicCommonInit(TRUE); if ( legic_select_card_iv(&card, iv) ) { isOK = 0; + msg = 1; goto OUT; } - if (len + offset >= card.cardsize) + if ( len + offset > card.cardsize) len = card.cardsize - offset; - setup_phase_reader(iv); - LED_B_ON(); - int r = 0; - // how about we write backwards instead. no need for this extra DCF check. - // index = len - cardsize - // stops uid 01234, - /* - len = 20 - offset = 5 - - index = 20+5 = 25 - if ( index > cardsize ) return -1; - - loop - write( data[index], index , card.addrsize); - --index; - end loop - */ - uint16_t index = len; - while(index > 4) { - - r = legic_write_byte( index, data[ index ], card.addrsize); - - if ( r ) { - Dbprintf("operation aborted @ 0x%03.3x", index); + while( len > 0 ) { + --len; + if ( !legic_write_byte( len + offset, data[len], card.addrsize) ) { + Dbprintf("operation failed | %02X | %02X | %02X", len + offset, len, data[len] ); isOK = 0; goto OUT; } - --index; WDT_HIT(); } - OUT: - cmd_send(CMD_ACK, isOK, 0,0,0,0); + cmd_send(CMD_ACK, isOK, msg,0,0,0); switch_off_tag_rwd(); LEDsoff(); } @@ -644,7 +613,7 @@ void LegicRfInfo(void){ uint8_t buf[sizeof(legic_card_select_t)] = {0x00}; legic_card_select_t *card = (legic_card_select_t*) buf; - LegicCommonInit(); + LegicCommonInit(FALSE); if ( legic_select_card(card) ) { cmd_send(CMD_ACK,0,0,0,0,0); @@ -685,31 +654,35 @@ static void frame_handle_tag(struct legic_frame const * const f) // log //uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)}; //LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE); - - cardmem = BigBuf_get_EM_addr(); - + //Dbprintf("ICE: enter frame_handle_tag: %02x ", f->bits); + /* First Part of Handshake (IV) */ if(f->bits == 7) { LED_C_ON(); // Reset prng timer - ResetTimer(prng_timer); + //ResetTimer(prng_timer); + ResetTicks(); // IV from reader. legic_prng_init(f->data); + Dbprintf("ICE: IV: %02x ", f->data); + // We should have three tagtypes with three different answers. - frame_send_tag(0x3d, 6); /* 0x3d^0x26 = 0x1B */ + legic_prng_forward(2); + //frame_send_tag(0x3d, 6); /* MIM1024 0x3d^0x26 = 0x1B */ + frame_send_tag(0x1d, 6); // MIM256 legic_state = STATE_IV; legic_read_count = 0; legic_prng_bc = 0; legic_prng_iv = f->data; - - ResetTimer(timer); - WaitUS(280); + //ResetTimer(timer); + //WaitUS(280); + WaitTicks(388); return; } @@ -721,7 +694,7 @@ static void frame_handle_tag(struct legic_frame const * const f) legic_state = STATE_CON; ResetTimer(timer); - WaitUS(200); + WaitTicks(300); return; } else { @@ -739,13 +712,14 @@ static void frame_handle_tag(struct legic_frame const * const f) uint16_t addr = f->data ^ key; addr >>= 1; uint8_t data = cardmem[addr]; - int hash = legic4Crc(LEGIC_READ, addr, data, 11) << 8; + + uint32_t crc = legic4Crc(LEGIC_READ, addr, data, 11) << 8; - legic_read_count++; - legic_prng_forward(legic_reqresp_drift); + //legic_read_count++; + //legic_prng_forward(legic_reqresp_drift); - frame_send_tag(hash | data, 12); - ResetTimer(timer); + frame_send_tag(crc | data, 12); + //ResetTimer(timer); legic_prng_forward(2); WaitTicks(330); return; @@ -753,7 +727,7 @@ static void frame_handle_tag(struct legic_frame const * const f) } /* Write */ - if(f->bits == 23) { + if (f->bits == 23 || f->bits == 21 ) { uint32_t key = get_key_stream(-1, 23); //legic_frame_drift, 23); uint16_t addr = f->data ^ key; addr >>= 1; @@ -767,7 +741,7 @@ static void frame_handle_tag(struct legic_frame const * const f) legic_state = STATE_DISCON; LED_C_OFF(); Dbprintf("write - addr: %x, data: %x", addr, data); - // should send a ACK within 3.5ms too + // should send a ACK after 3.6ms return; } @@ -776,11 +750,11 @@ static void frame_handle_tag(struct legic_frame const * const f) Dbprintf("IV: %03.3x", legic_prng_iv); } - legic_state = STATE_DISCON; - legic_read_count = 0; - SpinDelay(10); - LED_C_OFF(); - return; + legic_state = STATE_DISCON; + legic_read_count = 0; + WaitMS(10); + LED_C_OFF(); + return; } /* Read bit by bit untill full frame is received @@ -817,22 +791,41 @@ void LegicRfSimulate(int phase, int frame, int reqresp) * measure the time between two rising edges on DIN, and no encoding on the * subcarrier from card to reader, so we'll just shift out our verbatim data * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear, - * seems to be 300us-ish. + * seems to be 330us. */ int old_level = 0, active = 0; + volatile int32_t level = 0; + legic_state = STATE_DISCON; - legic_phase_drift = phase; legic_frame_drift = frame; legic_reqresp_drift = reqresp; + + /* to get the stream of bits from FPGA in sim mode.*/ FpgaDownloadAndGo(FPGA_BITSTREAM_HF); + // Set up the synchronous serial port + //FpgaSetupSsc(); + // connect Demodulated Signal to ADC: SetAdcMuxFor(GPIO_MUXSEL_HIPKD); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K); + //FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION); + + #define LEGIC_DMA_BUFFER 256 + // The DMA buffer, used to stream samples from the FPGA + //uint8_t *dmaBuf = BigBuf_malloc(LEGIC_DMA_BUFFER); + //uint8_t *data = dmaBuf; + // Setup and start DMA. + // if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER) ){ + // if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting"); + // return; + // } + //StartCountSspClk(); /* Bitbang the receiver */ - LINE_IN; + AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN; + AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN; // need a way to determine which tagtype we are simulating @@ -848,30 +841,62 @@ void LegicRfSimulate(int phase, int frame, int reqresp) LED_B_ON(); DbpString("Starting Legic emulator, press button to end"); - + + /* + * The mode FPGA_HF_SIMULATOR_MODULATE_212K works like this. + * - A 1-bit input to the FPGA becomes 8 pulses on 212kHz (fc/64) (18.88us). + * - A 0-bit input to the FPGA becomes an unmodulated time of 18.88us + * + * In this mode the SOF can be written as 00011101 = 0x1D + * The EOF can be written as 10111000 = 0xb8 + * A logic 1 is 01 + * A logic 0 is 10 + volatile uint8_t b; + uint8_t i = 0; + while( !BUTTON_PRESS() ) { + WDT_HIT(); + + // not sending anything. + if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { + AT91C_BASE_SSC->SSC_THR = 0x00; + } + + // receive + if ( AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY ) { + b = (uint8_t) AT91C_BASE_SSC->SSC_RHR; + bd[i] = b; + ++i; + // if(OutOfNDecoding(b & 0x0f)) + // *len = Uart.byteCnt; + } + + } + */ + while(!BUTTON_PRESS() && !usb_poll_validate_length()) { - volatile uint32_t level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN); + + level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN); uint32_t time = GET_TICKS; if (level != old_level) { - - if (level) { + if (level == 1) { - ResetTicks(); - + //Dbprintf("start, %u ", time); + StartTicks(); + // did we get a signal if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) { - /* 1 bit */ + // 1 bit emit(1); active = 1; LED_A_ON(); } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) { - /* 0 bit */ + // 0 bit emit(0); active = 1; LED_A_ON(); } else if (active) { - /* invalid */ + // invalid emit(-1); active = 0; LED_A_OFF(); @@ -879,8 +904,9 @@ void LegicRfSimulate(int phase, int frame, int reqresp) } } + /* Frame end */ - if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) { + if(time >= (RWD_TIME_1 + RWD_TIME_FUZZ) && active) { emit(-1); active = 0; LED_A_OFF(); @@ -891,19 +917,23 @@ void LegicRfSimulate(int phase, int frame, int reqresp) * shutdown in its status register. Reading the SR has the * side-effect of clearing any pending state in there. */ - if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) + //if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) + if(time >= (20 * RWD_TIME_1) ) StopTicks(); old_level = level; WDT_HIT(); - } +} WDT_HIT(); + DbpString("LEGIC Prime emulator stopped"); switch_off_tag_rwd(); + FpgaDisableSscDma(); LEDsoff(); cmd_send(CMD_ACK, 1, 0, 0, 0, 0); } + //----------------------------------------------------------------------------- // Code up a string of octets at layer 2 (including CRC, we don't generate // that here) so that they can be transmitted to the reader. Doesn't transmit