X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/fa57f6e12e23c7b78d24902926d1122b31cb2c67..5381b6fed52da1b7d1d3d07bb176555e02903029:/fpga/lo_read.v

diff --git a/fpga/lo_read.v b/fpga/lo_read.v
index b1fa7fc7..a6d077b9 100644
--- a/fpga/lo_read.v
+++ b/fpga/lo_read.v
@@ -13,7 +13,8 @@ module lo_read(
 	output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
 	input [7:0] adc_d, output adc_clk,
 	output ssp_frame, output ssp_din, output ssp_clk,
-	output dbg
+	output dbg,
+	input lf_field
 );
 
 reg [7:0] to_arm_shiftreg;
@@ -65,7 +66,7 @@ assign pwr_oe2 = 1'b0;
 assign pwr_oe3 = 1'b0;
 assign pwr_oe4 = 1'b0;
 // this is the antenna driver signal
-assign pwr_lo = pck_divclk;
+assign pwr_lo = lf_field & pck_divclk;
 // ADC clock out of phase with antenna driver
 assign adc_clk = ~pck_divclk;
 // ADC clock also routed to debug pin