X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/fa57f6e12e23c7b78d24902926d1122b31cb2c67..564c9ae2b68afc0d8b0455fb9b9d2aba0ca6c574:/fpga/fpga_lf.v

diff --git a/fpga/fpga_lf.v b/fpga/fpga_lf.v
index 1e20aa90..1b7a1127 100644
--- a/fpga/fpga_lf.v
+++ b/fpga/fpga_lf.v
@@ -1,13 +1,4 @@
 //-----------------------------------------------------------------------------
-// The FPGA is responsible for interfacing between the A/D, the coil drivers,
-// and the ARM. In the low-frequency modes it passes the data straight
-// through, so that the ARM gets raw A/D samples over the SSP. In the high-
-// frequency modes, the FPGA might perform some demodulation first, to
-// reduce the amount of data that we must send to the ARM.
-//
-// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
-// could be improved.
-//
 // Jonathan Westhues, March 2006
 // iZsh <izsh at fail0verflow.com>, June 2014
 //-----------------------------------------------------------------------------
@@ -39,15 +30,20 @@ module fpga_lf(
 reg [15:0] shift_reg;
 reg [7:0] divisor;
 reg [7:0] conf_word;
+reg [7:0] user_byte1;
 
-// We switch modes between transmitting to the 13.56 MHz tag and receiving
-// from it, which means that we must make sure that we can do so without
-// glitching, or else we will glitch the transmitted carrier.
 always @(posedge ncs)
 begin
 	case(shift_reg[15:12])
-		4'b0001: conf_word <= shift_reg[7:0];		// FPGA_CMD_SET_CONFREG
-		4'b0010: divisor <= shift_reg[7:0];		// FPGA_CMD_SET_DIVISOR
+		4'b0001:
+			begin
+				conf_word <= shift_reg[7:0];
+				if (shift_reg[7:0] == 8'b00000001) begin // LF edge detect
+					user_byte1 <= 127; // default threshold
+				end
+			end
+		4'b0010: divisor <= shift_reg[7:0];			// FPGA_CMD_SET_DIVISOR
+		4'b0011: user_byte1 <= shift_reg[7:0];		// FPGA_CMD_SET_USER_BYTE1
 	endcase
 end
 
@@ -60,11 +56,12 @@ begin
 	end
 end
 
-wire [2:0] major_mode;
-assign major_mode = conf_word[7:5];
+wire [2:0] major_mode = conf_word[7:5];
 
 // For the low-frequency configuration:
 wire lf_field = conf_word[0];
+wire lf_ed_toggle_mode = conf_word[1]; // for lo_edge_detect
+wire [7:0] lf_ed_threshold = user_byte1;
 
 //-----------------------------------------------------------------------------
 // And then we instantiate the modules corresponding to each of the FPGA's
@@ -80,7 +77,7 @@ lo_read lr(
 	lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
 	adc_d, lr_adc_clk,
 	lr_ssp_frame, lr_ssp_din, lr_ssp_clk,
-	lr_dbg
+	lr_dbg, lf_field
 );
 
 lo_passthru lp(
@@ -93,13 +90,14 @@ lo_passthru lp(
 );
 
 lo_edge_detect le(
-	pck0, pck_cnt, pck_divclk,
+	pck0, pck_divclk,
 	le_pwr_lo, le_pwr_hi, le_pwr_oe1, le_pwr_oe2, le_pwr_oe3, le_pwr_oe4,
 	adc_d, le_adc_clk,
 	le_ssp_frame, ssp_dout, le_ssp_clk,
 	cross_lo,
 	le_dbg,
-	lf_field
+	lf_field,
+	lf_ed_toggle_mode, lf_ed_threshold
 );
 
 // Major modes:
@@ -108,7 +106,7 @@ lo_edge_detect le(
 //   010 --  LF passthrough
 
 mux8 mux_ssp_clk		(major_mode, ssp_clk,   lr_ssp_clk,   le_ssp_clk,         1'b0,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
-mux8 mux_ssp_din		(major_mode, ssp_din,   lr_ssp_din,         1'b0,         1'b0,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
+mux8 mux_ssp_din		(major_mode, ssp_din,   lr_ssp_din,         1'b0,   lp_ssp_din,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
 mux8 mux_ssp_frame		(major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame,       1'b0,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0); 
 mux8 mux_pwr_oe1		(major_mode, pwr_oe1,   lr_pwr_oe1,   le_pwr_oe1,   lp_pwr_oe1,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
 mux8 mux_pwr_oe2		(major_mode, pwr_oe2,   lr_pwr_oe2,   le_pwr_oe2,   lp_pwr_oe2,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);