cvs.zerfleddert.de Git - proxmark3-svn/commit

]> cvs.zerfleddert.de Git - proxmark3-svn/commit - armsrc/iclass.c

author	pwpiwi <pwpiwi@users.noreply.github.com>
	Tue, 10 Sep 2019 16:18:54 +0000 (18:18 +0200)
committer	pwpiwi <pwpiwi@users.noreply.github.com>
	Wed, 11 Sep 2019 05:54:56 +0000 (07:54 +0200)
commit	a66f26da182040ac798a7c629d255cb86803e9c2
tree	f266b70e3c40fca5141fd78114da2dffa61f30c0	tree \| snapshot
parent	3d2c9c9b066c5a0b6a8dab467d86561223ddac10	commit \| diff

fix 'hf iclass sim':
* add simulation of block 3 and 4 reads
* add simulation of READ4 (4 blocks read)
* fixing TransmitTo15693Reader() (again)
* FPGA change (hi_simulate.v): avoid spp_clk phase changes
* some whitespace fixes

armsrc/iclass.c		diff \| blob \| blame \| history
armsrc/iso15693.c		diff \| blob \| blame \| history
armsrc/iso15693.h		diff \| blob \| blame \| history
fpga/fpga_hf.bit		diff \| blob \| blame \| history
fpga/hi_simulate.v		diff \| blob \| blame \| history

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