From: iceman1001 <iceman@iuse.se>
Date: Mon, 26 Sep 2016 19:38:19 +0000 (+0200)
Subject: CHG:   @ikarus23 removed all missleadning warnings for GCC6.1.1.
X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/commitdiff_plain/3c6542087e2a0f92f5c1024b812aac969253a764?ds=sidebyside

CHG:   @ikarus23 removed all missleadning warnings for GCC6.1.1.
---

diff --git a/bootrom/bootrom.c b/bootrom/bootrom.c
index 4437b9f2..44bfaba6 100644
--- a/bootrom/bootrom.c
+++ b/bootrom/bootrom.c
@@ -49,8 +49,7 @@ static void ConfigClocks(void)
         PMC_MAIN_OSC_STARTUP_DELAY(8);
 
 	// wait for main oscillator to stabilize
-	while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) )
-		;
+	while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) ) {};
 
     // PLL output clock frequency in range  80 - 160 MHz needs CKGR_PLL = 00
     // PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
@@ -63,8 +62,7 @@ static void ConfigClocks(void)
 		PMC_PLL_USB_DIVISOR(1);
 
 	// wait for PLL to lock
-	while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) )
-		;
+	while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) ) {};
 
 	// we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
 	// datasheet recommends that this register is programmed in two operations
@@ -72,15 +70,13 @@ static void ConfigClocks(void)
     AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
 
 	// wait for main clock ready signal
-	while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
-		;
+	while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ) {};
 
 	// set the source to PLL
     AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK;
 
 	// wait for main clock ready signal
-	while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
-		;
+	while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ) {};
 }
 
 static void Fatal(void) {
@@ -199,8 +195,7 @@ static void flash_mode(int externally_entered)
 	size_t rx_len;
 
 	usb_enable();
-	for (volatile size_t i=0; i<0x100000; i++)
-		;
+	for (volatile size_t i=0; i<0x100000; i++) {};
 
 	for(;;) {
 		WDT_HIT();
diff --git a/client/cmdhf14a.c b/client/cmdhf14a.c
index fe308746..b1e894cd 100644
--- a/client/cmdhf14a.c
+++ b/client/cmdhf14a.c
@@ -655,14 +655,17 @@ int CmdHF14ACmdRaw(const char *cmd) {
 		c.arg[2] = 13560000 / 1000 / (8*16) * timeout; // timeout in ETUs (time to transfer 1 bit, approx. 9.4 us)
 	}
 
-    if(power)
+    if(power) {
         c.arg[0] |= ISO14A_NO_DISCONNECT;
-
-    if(datalen>0)
+	}
+	
+    if(datalen>0) {
         c.arg[0] |= ISO14A_RAW;
-
-	if(topazmode)
+	}
+	
+	if(topazmode) {
 		c.arg[0] |= ISO14A_TOPAZMODE;
+	}
 			
 	// Max buffer is USB_CMD_DATA_SIZE
 	datalen = (datalen > USB_CMD_DATA_SIZE) ? USB_CMD_DATA_SIZE : datalen;
diff --git a/common/lfdemod.c b/common/lfdemod.c
index e748fddb..2b1373ee 100644
--- a/common/lfdemod.c
+++ b/common/lfdemod.c
@@ -81,12 +81,9 @@ size_t removeParity(uint8_t *BitStream, size_t startIdx, uint8_t pLen, uint8_t p
 		j--; // overwrite parity with next data
 		// if parity fails then return 0
 		switch (pType) {
-			case 3: if (BitStream[j]==1) return 0; break; //should be 0 spacer bit
-			case 2: if (BitStream[j]==0) return 0; break; //should be 1 spacer bit
-			default: //test parity
-				if (parityTest(parityWd, pLen, pType) == 0) 
-					return 0; 
-				break;
+			case 3:  if (BitStream[j]==1) { return 0 }; break; //should be 0 spacer bit
+			case 2:  if (BitStream[j]==0) { return 0 }; break; //should be 1 spacer bit
+			default: if (parityTest(parityWd, pLen, pType) == 0) { return 0; } break; //test parity
 		}
 		bitCnt+=(pLen-1);
 		parityWd = 0;