From: iceman1001 <iceman@iuse.se>
Date: Wed, 24 Aug 2016 10:37:31 +0000 (+0200)
Subject: FIX: the underlaying bug on deviceside code.  The SSPCLOCK wasn't reset to zero somet... 
X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/commitdiff_plain/63a1d80130db41e4d18bce2e6ada85c6a2c569ac?ds=sidebyside;hp=a1ab594e244c1554b2e997efa8813e8ec3b80017

FIX: the underlaying bug on deviceside code.  The SSPCLOCK wasn't reset to zero sometimes. More specific,  TC2 wasn't reset cause all sorts of timing issues for the device side randomly.  Like 'hf mf mifare',  like iclass,  like 'hf mf sim'  etc etc.
---

diff --git a/armsrc/util.c b/armsrc/util.c
index 1efc2b2b..b4d3dec5 100644
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -400,9 +400,9 @@ void StartCountSspClk() {
 							| AT91C_TC_WAVE 				// Waveform Mode
 							| AT91C_TC_WAVESEL_UP;	 		// just count
 
-	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;				// enable TC0
-	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;				// enable TC1
-	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;				// enable TC2
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;				// enable and reset TC0
+	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;				// enable and reset TC1
+	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;				// enable and reset TC2
 
 	// synchronize the counter with the ssp_frame signal. 
 	// Note: FPGA must be in any iso14443 mode, otherwise the frame signal would not be present 
@@ -420,7 +420,13 @@ void StartCountSspClk() {
 
 	// The high word of the counter (TC2) will not reset until the low word (TC0) overflows. 
 	// Therefore need to wait quite some time before we can use the counter.
-	while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
+	while (AT91C_BASE_TC2->TC_CV >= 1);
+}
+void ResetSspClk(void) {	
+	//enable clock of timer and software trigger
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
+	AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
+	AT91C_BASE_TC2->TC_CCR = AT91C_TC_SWTRG;
 }
 
 uint32_t RAMFUNC GetCountSspClk(){