From: AntiCat <contiki@anticat.ch>
Date: Tue, 14 Aug 2018 07:24:02 +0000 (+0200)
Subject: fix: 32bit tick timer based on TC0 and TC1 (#653)
X-Git-Tag: v3.1.0~31
X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/commitdiff_plain/8ff31e935d19bc53dd8f27877b7450cafba4a942?ds=sidebyside;hp=8ff31e935d19bc53dd8f27877b7450cafba4a942

fix: 32bit tick timer based on TC0 and TC1 (#653)

TC1 counts the number of TC0 overflows (carry bits).
In random conditions TC1 would return or stay at zero,
instead of counting up. This due to the behavior of the
reset signal.

SAM7S Series Datasheet, 33.5.6 Trigger:
Regardless of the trigger used, it will be taken into account
at the following active edge of the selected clock. This means
that the counter value can be read differently from zero just
after a trigger, especially when a low frequency signal is
selected as the clock.

The new code first prepares TC1 and asserts TC1 trigger and
then prepares TC0 and asserts TC0 trigger. The TC0 start-up
will reset TC1.
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