From: iceman1001 <iceman@iuse.se>
Date: Fri, 29 Apr 2016 20:23:32 +0000 (+0200)
Subject: CHG: the 14b is getting better, since I added the fpga waiting signaling I found...
X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/commitdiff_plain/ffeb77fdc6c57449b6a5607b4468eb981a05dd4e
CHG: the 14b is getting better, since I added the fpga waiting signaling I found in "14a emgetcmd" etc.
---
diff --git a/armsrc/iso14443b.c b/armsrc/iso14443b.c
index a393ed58..0c887a25 100644
--- a/armsrc/iso14443b.c
+++ b/armsrc/iso14443b.c
@@ -21,7 +21,8 @@
#define TR2 0
// 4sample
-#define SEND4STUFFBIT(x) ToSendStuffBit(x);ToSendStuffBit(x);ToSendStuffBit(x);ToSendStuffBit(x);
+//#define SEND4STUFFBIT(x) ToSendStuffBit(x);ToSendStuffBit(x);ToSendStuffBit(x);ToSendStuffBit(x);
+#define SEND4STUFFBIT(x) ToSendStuffBit(x);
static void switch_off(void);
@@ -403,13 +404,25 @@ static int GetIso14443bCommandFromReader(uint8_t *received, uint16_t *len) {
// Signal field is off with the appropriate LED
LED_D_OFF();
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
-
+
StartCountSspClk();
+ volatile uint8_t b;
+
+ // clear receiving shift register and holding register
+ // What does this loop do? Is it TR1?
+ for(uint8_t c = 0; c < 10;) {
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+ AT91C_BASE_SSC->SSC_THR = 0xFF;
+ ++c;
+ }
+ }
+
// Now run a `software UART' on the stream of incoming samples.
UartInit(received);
-
- uint8_t mask, b = 0;
+
+ b = 0;
+ uint8_t mask;
while( !BUTTON_PRESS() ) {
WDT_HIT();
@@ -426,27 +439,61 @@ static int GetIso14443bCommandFromReader(uint8_t *received, uint16_t *len) {
return FALSE;
}
+void ClearFpgaShiftingRegisters(void){
+
+ volatile uint8_t b;
+
+ // clear receiving shift register and holding register
+ while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
+ b = AT91C_BASE_SSC->SSC_RHR; (void) b;
+
+ while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
+ b = AT91C_BASE_SSC->SSC_RHR; (void) b;
+
+
+ // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
+ for (uint8_t j = 0; j < 5; j++) { // allow timeout - better late than never
+ while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
+ if (AT91C_BASE_SSC->SSC_RHR) break;
+ }
+
+ // Clear TXRDY:
+ AT91C_BASE_SSC->SSC_THR = 0xFF;
+}
+
+void WaitForFpgaDelayQueueIsEmpty( uint16_t delay ){
+ // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
+ uint8_t fpga_queued_bits = delay >> 3; // twich /8 ?? >>3,
+ for (uint8_t i = 0; i <= fpga_queued_bits/8 + 1; ) {
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+ AT91C_BASE_SSC->SSC_THR = 0xFF;
+ i++;
+ }
+ }
+}
static void TransmitFor14443b_AsTag( uint8_t *response, uint16_t len) {
// Signal field is off with the appropriate LED
LED_D_OFF();
+ uint16_t fpgasendQueueDelay = 0;
// Modulate BPSK
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
- // 8 ETU / 8bits. 8/4= 2 etus.
- AT91C_BASE_SSC->SSC_THR = 0XFF;
-
+ ClearFpgaShiftingRegisters();
+
FpgaSetupSsc();
// Transmit the response.
for(uint16_t i = 0; i < len;) {
if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
- AT91C_BASE_SSC->SSC_THR = response[i];
- ++i;
+ AT91C_BASE_SSC->SSC_THR = response[++i];
+ fpgasendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
}
}
+
+ WaitForFpgaDelayQueueIsEmpty(fpgasendQueueDelay);
}
//-----------------------------------------------------------------------------
// Main loop of simulated tag: receive commands from reader, decide what
@@ -537,13 +584,10 @@ void SimulateIso14443bTag(uint32_t pupi) {
// REQ or WUP request in ANY state
// WUP in HALTED state
if (len == 5 ) {
- if ( (receivedCmd[0] == ISO14443B_REQB && (receivedCmd[2] & 0x8)== 0x8 && cardSTATE != SIM_HALTED) ||
- (receivedCmd[0] == ISO14443B_REQB && (receivedCmd[2] & 0x8)== 0) ){
-
- TransmitFor14443b_AsTag( encodedATQB, encodedATQBLen );
- LogTrace(respATQB, sizeof(respATQB), 0, 0, NULL, FALSE);
+ if ( (receivedCmd[0] == ISO14443B_REQB && (receivedCmd[2] & 0x8)== 0x8 && cardSTATE == SIM_HALTED) ||
+ receivedCmd[0] == ISO14443B_REQB ){
+ LogTrace(receivedCmd, len, 0, 0, NULL, TRUE);
cardSTATE = SIM_SELECTING;
- continue;
}
}
@@ -567,7 +611,7 @@ void SimulateIso14443bTag(uint32_t pupi) {
case SIM_SELECTING: {
TransmitFor14443b_AsTag( encodedATQB, encodedATQBLen );
LogTrace(respATQB, sizeof(respATQB), 0, 0, NULL, FALSE);
- cardSTATE = SIM_IDLE;
+ cardSTATE = SIM_WORK;
break;
}
case SIM_HALTING: {
diff --git a/armsrc/iso14443b.h b/armsrc/iso14443b.h
index 1ed439ac..75fdab55 100644
--- a/armsrc/iso14443b.h
+++ b/armsrc/iso14443b.h
@@ -32,6 +32,9 @@ uint8_t iso14443b_apdu(uint8_t const *message, size_t message_length, uint8_t *r
uint8_t iso14443b_select_card(iso14b_card_select_t* card);
uint8_t iso14443b_select_card_srx(iso14b_card_select_t* card);
+// testfunctions
+void WaitForFpgaDelayQueueIsEmpty( uint16_t delay );
+void ClearFpgaShiftingRegisters(void);
// States for 14B SIM command
#define SIM_NOFIELD 0
diff --git a/client/lualibs/read14b.lua b/client/lualibs/read14b.lua
index 11664f34..9d287266 100644
--- a/client/lualibs/read14b.lua
+++ b/client/lualibs/read14b.lua
@@ -13,7 +13,7 @@
-- Loads the commands-library
local cmds = require('commands')
local utils = require('utils')
-local TIMEOUT = 2000
+local TIMEOUT = 2500
local ISO14B_COMMAND = {
ISO14B_CONNECT = 1,
ISO14B_DISCONNECT = 2,
diff --git a/client/scripts/calypso.lua b/client/scripts/calypso.lua
index 9221c029..ed9efa1f 100644
--- a/client/scripts/calypso.lua
+++ b/client/scripts/calypso.lua
@@ -52,6 +52,7 @@ local function calypso_parse(result)
local r = Command.parse(result)
local len = r.arg2 * 2
r.data = string.sub(r.data, 0, len);
+ print('GOT:', r.data)
if r.arg1 == 0 then
return r, nil
end
@@ -162,7 +163,8 @@ local function calypso_apdu_status(apdu)
end
local _calypso_cmds = {
- ["01.Select ICC file"] = '0294 a4 080004 3f00 0002',
+ ["01.Select ICC file"] = '0294 a4 00 0002 3f00',
+ --["01.Select ICC file"] = '0294 a4 080004 3f00 0002',
["02.ICC"] = '0294 b2 01 041d',
["03.Select EnvHol file"] = '0294 a4 080004 2000 2001',
["04.EnvHol1"] = '0294 b2 01 041d',