From bad6eab230c6cc08589c7756157ca6c50ed3fdad Mon Sep 17 00:00:00 2001
From: d18c7db <d18c7db@ef4ab9da-24cd-11de-8aaa-f3a34680c41f>
Date: Wed, 3 Mar 2010 02:27:14 +0000
Subject: [PATCH 1/1] Fix possible type casting issue. Add another JTAG config
 file :)

---
 armsrc/iso14443a.c             |  2 +-
 tools/at91sam7s512-jtagkey.cfg | 41 ++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+), 1 deletion(-)
 create mode 100644 tools/at91sam7s512-jtagkey.cfg

diff --git a/armsrc/iso14443a.c b/armsrc/iso14443a.c
index 2e91d263..c0bdb742 100644
--- a/armsrc/iso14443a.c
+++ b/armsrc/iso14443a.c
@@ -77,7 +77,7 @@ static void AppendCrc14443a(uint8_t* data, int len)
   ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
 }
 
-int LogTrace(const uint8_t * btBytes, int iLen, int iSamples, uint32_t dwParity, int bReader)
+int LogTrace(const uint8_t * btBytes, size_t iLen, int iSamples, uint32_t dwParity, int bReader)
 {
   // Return when trace is full
   if (traceLen >= TRACE_LENGTH) return FALSE;
diff --git a/tools/at91sam7s512-jtagkey.cfg b/tools/at91sam7s512-jtagkey.cfg
new file mode 100644
index 00000000..3bcc5120
--- /dev/null
+++ b/tools/at91sam7s512-jtagkey.cfg
@@ -0,0 +1,41 @@
+#define our ports
+telnet_port 4444
+gdb_port 3333
+
+#commands specific to the Amontec JTAGKey
+interface ft2232
+ft2232_device_desc "Amontec JTAGkey A"
+ft2232_layout jtagkey
+ft2232_vid_pid 0x0403 0xcff8
+jtag_khz 200
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+#reset_config <signals> [combination] [trst_type] [srst_type]
+reset_config srst_only srst_pulls_trst
+
+jtag newtap sam7x cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x3f0f0f0f
+
+target create sam7x.cpu arm7tdmi -endian little -chain-position sam7x.cpu -variant arm7tdmi
+
+sam7x.cpu configure -event reset-init {
+	soft_reset_halt
+	mww 0xfffffd00 0xa5000004	# RSTC_CR: Reset peripherals
+	mww 0xfffffd44 0x00008000	# WDT_MR: disable watchdog
+	mww 0xfffffd08 0xa5000001	# RSTC_MR enable user reset
+	mww 0xfffffc20 0x00005001	# CKGR_MOR : enable the main oscillator
+	sleep 10
+	mww 0xfffffc2c 0x000b1c02	# CKGR_PLLR: 16MHz * 12/2 = 96MHz
+	sleep 10
+	mww 0xfffffc30 0x00000007	# PMC_MCKR : MCK = PLL / 2 = 48 MHz
+	sleep 10
+	mww 0xffffff60 0x00480100	# MC_FMR: flash mode (FWS=1,FMCN=72)
+	sleep 100
+}
+
+gdb_memory_map enable
+gdb_breakpoint_override hard
+armv4_5 core_state arm
+
+sam7x.cpu configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x10000 -work-area-backup 0
+flash bank at91sam7 0x100000 0x40000 0 4 sam7x.cpu
-- 
2.39.5