[raggedstone] / dhwk / source / top.vhd

-- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007\r
\r
\r
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LIBRARY ieee;\r
\r
USE ieee.std_logic_1164.ALL;\r
USE ieee.numeric_std.ALL;\r
\r
\r
entity dhwk is\r
      Port ( KONST_1 : In    std_logic;\r
             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
             PCI_FRAMEn : In    std_logic;\r
             PCI_IDSEL : In    std_logic;\r
             PCI_IRDYn : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
--             SERIAL_IN : In    std_logic;\r
--             SPC_RDY_IN : In    std_logic;\r
             TAST_RESn : In    std_logic;\r
             TAST_SETn : In    std_logic;\r
             LED_2 : out    std_logic;\r
             LED_3 : out    std_logic;\r
             LED_4 : out    std_logic;\r
             LED_5 : out    std_logic;\r
              PCI_AD : InOut std_logic_vector (31 downto 0);\r
             PCI_PAR : InOut std_logic;\r
             PCI_DEVSELn : Out   std_logic;\r
             PCI_INTAn : Out   std_logic;\r
             PCI_PERRn : Out   std_logic;\r
             PCI_SERRn : Out   std_logic;\r
             PCI_STOPn : Out   std_logic;\r
             PCI_TRDYn : Out   std_logic;\r
--             SERIAL_OUT : Out   std_logic;\r
--             SPC_RDY_OUT : Out   std_logic;\r
             TB_IDSEL : Out   std_logic;\r
             TB_nDEVSEL : Out   std_logic;\r
             TB_nINTA : Out   std_logic );\r
end dhwk;\r
\r
architecture SCHEMATIC of dhwk is\r
\r
   SIGNAL gnd : std_logic := '0';\r
   SIGNAL vcc : std_logic := '1';\r
\r
   signal READ_XX7_6 : std_logic;\r
   signal  RESERVE : std_logic;\r
   signal SR_ERROR : std_logic;\r
   signal  R_ERROR : std_logic;\r
   signal  S_ERROR : std_logic;\r
   signal WRITE_XX3_2 : std_logic;\r
   signal WRITE_XX5_4 : std_logic;\r
   signal WRITE_XX7_6 : std_logic;\r
   signal READ_XX1_0 : std_logic;\r
   signal READ_XX3_2 : std_logic;\r
   signal    INTAn : std_logic;\r
   signal    TRDYn : std_logic;\r
   signal READ_XX5_4 : std_logic;\r
   signal  DEVSELn : std_logic;\r
   signal FIFO_RDn : std_logic;\r
   signal WRITE_XX1_0 : std_logic;\r
   signal REG_OUT_XX6 : std_logic_vector (7 downto 0);\r
   signal SYNC_FLAG : std_logic_vector (7 downto 0);\r
   signal  INT_REG : std_logic_vector (7 downto 0);\r
   signal REVISON_ID : std_logic_vector (7 downto 0);\r
   signal VENDOR_ID : std_logic_vector (15 downto 0);\r
   signal READ_SEL : std_logic_vector (1 downto 0);\r
   signal   AD_REG : std_logic_vector (31 downto 0);\r
   signal REG_OUT_XX7 : std_logic_vector (7 downto 0);\r
   signal R_EFn : std_logic;\r
   signal R_FFn : std_logic;\r
   signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
   signal R_HFn : std_logic;\r
   signal S_EFn : std_logic;\r
   signal S_FFn : std_logic;\r
   signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
   signal S_HFn : std_logic;\r
   signal R_FIFO_D_IN : std_logic_vector (7 downto 0);\r
   signal R_FIFO_READn : std_logic;\r
   signal R_FIFO_RESETn : std_logic;\r
   signal R_FIFO_RTn : std_logic;\r
   signal R_FIFO_WRITEn : std_logic;\r
   signal S_FIFO_D_IN : std_logic_vector (7 downto 0);\r
   signal S_FIFO_READn : std_logic;\r
   signal S_FIFO_RESETn : std_logic;\r
   signal S_FIFO_RTn : std_logic;\r
   signal S_FIFO_WRITEn : std_logic;\r
   signal SERIAL_IN : std_logic;\r
   signal SPC_RDY_IN : std_logic;\r
   signal SERIAL_OUT : std_logic;\r
   signal SPC_RDY_OUT : std_logic;\r
   signal watch : std_logic;\r
   signal control0       : std_logic_vector(35 downto 0);\r
   signal data       : std_logic_vector(35 downto 0);\r
   signal trig0      : std_logic_vector(7 downto 0);\r
\r
   component MESS_1_TB\r
      Port ( DEVSELn : In    std_logic;\r
               INTAn : In    std_logic;\r
             KONST_1 : In    std_logic;\r
             PCI_IDSEL : In    std_logic;\r
             REG_OUT_XX7 : In    std_logic_vector (7 downto 0);\r
             TB_DEVSELn : Out   std_logic;\r
             TB_INTAn : Out   std_logic;\r
             TB_PCI_IDSEL : Out   std_logic );\r
   end component;\r
\r
   component VEN_REV_ID\r
      Port (  REV_ID : Out   std_logic_vector (7 downto 0);\r
              VEN_ID : Out   std_logic_vector (15 downto 0) );\r
   end component;\r
\r
   component INTERRUPT\r
      Port ( INT_IN_0 : In    std_logic;\r
             INT_IN_1 : In    std_logic;\r
             INT_IN_2 : In    std_logic;\r
             INT_IN_3 : In    std_logic;\r
             INT_IN_4 : In    std_logic;\r
             INT_IN_5 : In    std_logic;\r
             INT_IN_6 : In    std_logic;\r
             INT_IN_7 : In    std_logic;\r
             INT_MASKE : In    std_logic_vector (7 downto 0);\r
             INT_RES : In    std_logic_vector (7 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
             READ_XX5_4 : In    std_logic;\r
               RESET : In    std_logic;\r
             TAST_RESn : In    std_logic;\r
             TAST_SETn : In    std_logic;\r
               TRDYn : In    std_logic;\r
             INT_REG : Out   std_logic_vector (7 downto 0);\r
               INTAn : Out   std_logic;\r
             PCI_INTAn : Out   std_logic );\r
   end component;\r
\r
   component FIFO_CONTROL\r
      Port ( FIFO_RDn : In    std_logic;\r
             FLAG_IN_0 : In    std_logic;\r
             FLAG_IN_4 : In    std_logic;\r
                HOLD : In    std_logic;\r
             KONST_1 : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
             PSC_ENABLE : In    std_logic;\r
               R_EFn : In    std_logic;\r
               R_FFn : In    std_logic;\r
               R_HFn : In    std_logic;\r
               RESET : In    std_logic;\r
               S_EFn : In    std_logic;\r
               S_FFn : In    std_logic;\r
             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
               S_HFn : In    std_logic;\r
             SERIAL_IN : In    std_logic;\r
             SPC_ENABLE : In    std_logic;\r
             SPC_RDY_IN : In    std_logic;\r
             WRITE_XX1_0 : In    std_logic;\r
             R_ERROR : Out   std_logic;\r
             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
             R_FIFO_READn : Out   std_logic;\r
             R_FIFO_RESETn : Out   std_logic;\r
             R_FIFO_RETRANSMITn : Out   std_logic;\r
             R_FIFO_WRITEn : Out   std_logic;\r
             RESERVE : Out   std_logic;\r
             S_ERROR : Out   std_logic;\r
             S_FIFO_READn : Out   std_logic;\r
             S_FIFO_RESETn : Out   std_logic;\r
             S_FIFO_RETRANSMITn : Out   std_logic;\r
             S_FIFO_WRITEn : Out   std_logic;\r
             SERIAL_OUT : Out   std_logic;\r
             SPC_RDY_OUT : Out   std_logic;\r
             SR_ERROR : Out   std_logic;\r
	     PAR_SER_IN : Out std_logic_vector (7 downto 0);\r
             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
   end component;\r
\r
   component PCI_TOP\r
      Port (    FLAG : In    std_logic_vector (7 downto 0);\r
             INT_REG : In    std_logic_vector (7 downto 0);\r
             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
             PCI_FRAMEn : In    std_logic;\r
             PCI_IDSEL : In    std_logic;\r
             PCI_IRDYn : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
             R_FIFO_Q : In    std_logic_vector (7 downto 0);\r
             REVISON_ID : In    std_logic_vector (7 downto 0);\r
             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
              PCI_AD : InOut std_logic_vector (31 downto 0);\r
             PCI_PAR : InOut std_logic;\r
              AD_REG : Out   std_logic_vector (31 downto 0);\r
             DEVSELn : Out   std_logic;\r
             FIFO_RDn : Out   std_logic;\r
             PCI_DEVSELn : Out   std_logic;\r
             PCI_PERRn : Out   std_logic;\r
             PCI_SERRn : Out   std_logic;\r
             PCI_STOPn : Out   std_logic;\r
             PCI_TRDYn : Out   std_logic;\r
             READ_SEL : Out   std_logic_vector (1 downto 0);\r
             READ_XX1_0 : Out   std_logic;\r
             READ_XX3_2 : Out   std_logic;\r
             READ_XX5_4 : Out   std_logic;\r
             READ_XX7_6 : Out   std_logic;\r
             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);\r
               TRDYn : Out   std_logic;\r
             WRITE_XX1_0 : Out   std_logic;\r
             WRITE_XX3_2 : Out   std_logic;\r
             WRITE_XX5_4 : Out   std_logic;\r
             WRITE_XX7_6 : Out   std_logic );\r
   end component;\r
\r
component fifo_generator_v3_2\r
        port (\r
        clk: IN std_logic;\r
        din: IN std_logic_VECTOR(7 downto 0);\r
        rd_en: IN std_logic;\r
        rst: IN std_logic;\r
        wr_en: IN std_logic;\r
        almost_empty: OUT std_logic;\r
        almost_full: OUT std_logic;\r
        dout: OUT std_logic_VECTOR(7 downto 0);\r
        empty: OUT std_logic;\r
        full: OUT std_logic;\r
        prog_full: OUT std_logic);\r
end component;\r
\r
component icon\r
port\r
	(\r
	 control0    :   out std_logic_vector(35 downto 0)\r
	);\r
end component;\r
\r
  component ila\r
    port\r
    (\r
      control     : in    std_logic_vector(35 downto 0);\r
      clk         : in    std_logic;\r
      data        : in    std_logic_vector(35 downto 0);\r
      trig0       : in    std_logic_vector(7 downto 0)\r
    );\r
  end component;\r
\r
\r
begin\r
	SERIAL_IN <= SERIAL_OUT;\r
	SPC_RDY_IN <= SPC_RDY_OUT;\r
	LED_2 <= TAST_RESn;\r
	LED_3 <= TAST_SETn;\r
	LED_4 <= '0';\r
	LED_5 <= not watch;\r
	PCI_INTAn <= watch;\r
	trig0(7 downto 0) <= (0 => watch, others => '0');\r
	data(0) <= watch;\r
	\r
	data(1) <= R_EFn;\r
	data(2) <= R_HFn;\r
	data(3) <= R_FFn;\r
	data(4) <= R_FIFO_READn;\r
	data(5) <= R_FIFO_RESETn;\r
	data(6) <= R_FIFO_RTn;\r
	data(7) <= R_FIFO_WRITEn;\r
	data(8) <= S_EFn;\r
	data(9) <= S_HFn;\r
	data(10) <= S_FFn;\r
	data(11) <= S_FIFO_READn;\r
	data(12) <= S_FIFO_RESETn;\r
	data(13) <= S_FIFO_RTn;\r
	data(14) <= S_FIFO_WRITEn;\r
	data(15) <= SERIAL_IN;\r
	data(16) <= SPC_RDY_IN;\r
	data(17) <= SERIAL_OUT;\r
	data(18) <= SPC_RDY_OUT;\r
\r
   I19 : MESS_1_TB\r
      Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
                 PCI_IDSEL=>PCI_IDSEL,\r
                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
                 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,\r
                 TB_PCI_IDSEL=>TB_IDSEL );\r
   I18 : VEN_REV_ID\r
      Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
                 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );\r
   I16 : INTERRUPT\r
      Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),\r
                 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,\r
                 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,\r
                 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
                 INT_RES(7 downto 0)=>AD_REG(7 downto 0),\r
                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
                 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
                 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
                 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
                 INTAn=>INTAn, PCI_INTAn=>watch);\r
   I14 : FIFO_CONTROL\r
      Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
                 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r
                 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),\r
                 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,\r
                 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,\r
                 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
                 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,\r
                 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,\r
                 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
                 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
                 R_FIFO_READn=>R_FIFO_READn,\r
                 R_FIFO_RESETn=>R_FIFO_RESETn,\r
                 R_FIFO_RETRANSMITn=>R_FIFO_RTn,\r
                 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,\r
                 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,\r
                 S_FIFO_RESETn=>S_FIFO_RESETn,\r
                 S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
                 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
                 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
		 PAR_SER_IN(7 downto 0)=>data(26 downto 19),\r
                 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
   I1 : PCI_TOP\r
      Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
                 INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
                 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
                 PCI_RSTn=>PCI_RSTn,\r
                 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),\r
                 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
                 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
                 PCI_PAR=>PCI_PAR,\r
                 AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
                 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
                 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,\r
                 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,\r
                 PCI_TRDYn=>PCI_TRDYn,\r
                 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
                 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
                 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,\r
                 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),\r
                 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
                 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,\r
                 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
                 WRITE_XX7_6=>WRITE_XX7_6 );\r
\r
receive_fifo : fifo_generator_v3_2\r
                port map (\r
                        clk => PCI_CLOCK,\r
                        din => R_FIFO_D_IN,\r
                        rd_en => not R_FIFO_READn,\r
                        rst => not R_FIFO_RESETn,\r
                        wr_en => not R_FIFO_WRITEn,\r
                        dout => R_FIFO_Q_OUT,\r
                        empty => R_EFn,\r
                        full => R_FFn,\r
                        prog_full => R_HFn);\r
\r
send_fifo : fifo_generator_v3_2\r
                port map (\r
                        clk => PCI_CLOCK,\r
                        din => S_FIFO_D_IN,\r
                        rd_en => not S_FIFO_READn,\r
                        rst => not S_FIFO_RESETn,\r
                        wr_en => not S_FIFO_WRITEn,\r
                        dout => S_FIFO_Q_OUT,\r
                        empty => S_EFn,\r
                        full => S_FFn,\r
                        prog_full => S_HFn);\r
\r
  i_icon : icon\r
      port map\r
          (\r
	        control0    => control0\r
	  );\r
\r
  i_ila : ila\r
    port map\r
    (\r
      control   => control0,\r
      clk       => PCI_CLOCK,\r
      data      => data,\r
      trig0     => trig0\r
    );\r
end SCHEMATIC;\r
Commit	Line	Data
377c0242	1	-- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007\r
	2	\r
	3	\r
	4	\r
	5	LIBRARY ieee;\r
	6	\r
	7	USE ieee.std_logic_1164.ALL;\r
	8	USE ieee.numeric_std.ALL;\r
	9	\r
	10	\r
62946980	11	entity dhwk is\r
377c0242	12	Port ( KONST_1 : In std_logic;\r
	13	PCI_CBEn : In std_logic_vector (3 downto 0);\r
	14	PCI_CLOCK : In std_logic;\r
	15	PCI_FRAMEn : In std_logic;\r
	16	PCI_IDSEL : In std_logic;\r
	17	PCI_IRDYn : In std_logic;\r
	18	PCI_RSTn : In std_logic;\r
257c0fc1	19	-- SERIAL_IN : In std_logic;\r
257c0fc1	20	-- SPC_RDY_IN : In std_logic;\r
377c0242	21	TAST_RESn : In std_logic;\r
377c0242	22	TAST_SETn : In std_logic;\r
bba7a6d5	23	LED_2 : out std_logic;\r
	24	LED_3 : out std_logic;\r
	25	LED_4 : out std_logic;\r
	26	LED_5 : out std_logic;\r
377c0242	27	PCI_AD : InOut std_logic_vector (31 downto 0);\r
	28	PCI_PAR : InOut std_logic;\r
	29	PCI_DEVSELn : Out std_logic;\r
	30	PCI_INTAn : Out std_logic;\r
	31	PCI_PERRn : Out std_logic;\r
	32	PCI_SERRn : Out std_logic;\r
	33	PCI_STOPn : Out std_logic;\r
	34	PCI_TRDYn : Out std_logic;\r
257c0fc1	35	-- SERIAL_OUT : Out std_logic;\r
257c0fc1	36	-- SPC_RDY_OUT : Out std_logic;\r
377c0242	37	TB_IDSEL : Out std_logic;\r
	38	TB_nDEVSEL : Out std_logic;\r
	39	TB_nINTA : Out std_logic );\r
62946980	40	end dhwk;\r
377c0242	41	\r
62946980	42	architecture SCHEMATIC of dhwk is\r
377c0242	43	\r
	44	SIGNAL gnd : std_logic := '0';\r
	45	SIGNAL vcc : std_logic := '1';\r
	46	\r
	47	signal READ_XX7_6 : std_logic;\r
	48	signal RESERVE : std_logic;\r
	49	signal SR_ERROR : std_logic;\r
	50	signal R_ERROR : std_logic;\r
	51	signal S_ERROR : std_logic;\r
	52	signal WRITE_XX3_2 : std_logic;\r
	53	signal WRITE_XX5_4 : std_logic;\r
	54	signal WRITE_XX7_6 : std_logic;\r
	55	signal READ_XX1_0 : std_logic;\r
	56	signal READ_XX3_2 : std_logic;\r
	57	signal INTAn : std_logic;\r
	58	signal TRDYn : std_logic;\r
	59	signal READ_XX5_4 : std_logic;\r
	60	signal DEVSELn : std_logic;\r
	61	signal FIFO_RDn : std_logic;\r
	62	signal WRITE_XX1_0 : std_logic;\r
	63	signal REG_OUT_XX6 : std_logic_vector (7 downto 0);\r
	64	signal SYNC_FLAG : std_logic_vector (7 downto 0);\r
	65	signal INT_REG : std_logic_vector (7 downto 0);\r
	66	signal REVISON_ID : std_logic_vector (7 downto 0);\r
	67	signal VENDOR_ID : std_logic_vector (15 downto 0);\r
	68	signal READ_SEL : std_logic_vector (1 downto 0);\r
	69	signal AD_REG : std_logic_vector (31 downto 0);\r
	70	signal REG_OUT_XX7 : std_logic_vector (7 downto 0);\r
2825d08e	71	signal R_EFn : std_logic;\r
	72	signal R_FFn : std_logic;\r
	73	signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
	74	signal R_HFn : std_logic;\r
	75	signal S_EFn : std_logic;\r
	76	signal S_FFn : std_logic;\r
	77	signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
	78	signal S_HFn : std_logic;\r
	79	signal R_FIFO_D_IN : std_logic_vector (7 downto 0);\r
	80	signal R_FIFO_READn : std_logic;\r
	81	signal R_FIFO_RESETn : std_logic;\r
	82	signal R_FIFO_RTn : std_logic;\r
	83	signal R_FIFO_WRITEn : std_logic;\r
	84	signal S_FIFO_D_IN : std_logic_vector (7 downto 0);\r
	85	signal S_FIFO_READn : std_logic;\r
	86	signal S_FIFO_RESETn : std_logic;\r
	87	signal S_FIFO_RTn : std_logic;\r
	88	signal S_FIFO_WRITEn : std_logic;\r
257c0fc1	89	signal SERIAL_IN : std_logic;\r
	90	signal SPC_RDY_IN : std_logic;\r
	91	signal SERIAL_OUT : std_logic;\r
	92	signal SPC_RDY_OUT : std_logic;\r
bba7a6d5	93	signal watch : std_logic;\r
1afff8d4	94	signal control0 : std_logic_vector(35 downto 0);\r
a76e12bd	95	signal data : std_logic_vector(35 downto 0);\r
1afff8d4	96	signal trig0 : std_logic_vector(7 downto 0);\r
377c0242	97	\r
	98	component MESS_1_TB\r
	99	Port ( DEVSELn : In std_logic;\r
	100	INTAn : In std_logic;\r
	101	KONST_1 : In std_logic;\r
	102	PCI_IDSEL : In std_logic;\r
	103	REG_OUT_XX7 : In std_logic_vector (7 downto 0);\r
	104	TB_DEVSELn : Out std_logic;\r
	105	TB_INTAn : Out std_logic;\r
	106	TB_PCI_IDSEL : Out std_logic );\r
	107	end component;\r
	108	\r
	109	component VEN_REV_ID\r
	110	Port ( REV_ID : Out std_logic_vector (7 downto 0);\r
	111	VEN_ID : Out std_logic_vector (15 downto 0) );\r
	112	end component;\r
	113	\r
	114	component INTERRUPT\r
	115	Port ( INT_IN_0 : In std_logic;\r
	116	INT_IN_1 : In std_logic;\r
	117	INT_IN_2 : In std_logic;\r
	118	INT_IN_3 : In std_logic;\r
	119	INT_IN_4 : In std_logic;\r
	120	INT_IN_5 : In std_logic;\r
	121	INT_IN_6 : In std_logic;\r
	122	INT_IN_7 : In std_logic;\r
	123	INT_MASKE : In std_logic_vector (7 downto 0);\r
	124	INT_RES : In std_logic_vector (7 downto 0);\r
	125	PCI_CLOCK : In std_logic;\r
	126	PCI_RSTn : In std_logic;\r
	127	READ_XX5_4 : In std_logic;\r
	128	RESET : In std_logic;\r
	129	TAST_RESn : In std_logic;\r
	130	TAST_SETn : In std_logic;\r
	131	TRDYn : In std_logic;\r
	132	INT_REG : Out std_logic_vector (7 downto 0);\r
	133	INTAn : Out std_logic;\r
	134	PCI_INTAn : Out std_logic );\r
	135	end component;\r
	136	\r
	137	component FIFO_CONTROL\r
	138	Port ( FIFO_RDn : In std_logic;\r
	139	FLAG_IN_0 : In std_logic;\r
	140	FLAG_IN_4 : In std_logic;\r
	141	HOLD : In std_logic;\r
	142	KONST_1 : In std_logic;\r
	143	PCI_CLOCK : In std_logic;\r
	144	PSC_ENABLE : In std_logic;\r
	145	R_EFn : In std_logic;\r
	146	R_FFn : In std_logic;\r
	147	R_HFn : In std_logic;\r
	148	RESET : In std_logic;\r
	149	S_EFn : In std_logic;\r
	150	S_FFn : In std_logic;\r
	151	S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
	152	S_HFn : In std_logic;\r
	153	SERIAL_IN : In std_logic;\r
	154	SPC_ENABLE : In std_logic;\r
	155	SPC_RDY_IN : In std_logic;\r
	156	WRITE_XX1_0 : In std_logic;\r
	157	R_ERROR : Out std_logic;\r
	158	R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
	159	R_FIFO_READn : Out std_logic;\r
	160	R_FIFO_RESETn : Out std_logic;\r
161	R_FIFO_RETRANSMITn : Out std_logic;\r
162	R_FIFO_WRITEn : Out std_logic;\r
163	RESERVE : Out std_logic;\r
164	S_ERROR : Out std_logic;\r
165	S_FIFO_READn : Out std_logic;\r
166	S_FIFO_RESETn : Out std_logic;\r
167	S_FIFO_RETRANSMITn : Out std_logic;\r
168	S_FIFO_WRITEn : Out std_logic;\r
169	SERIAL_OUT : Out std_logic;\r
170	SPC_RDY_OUT : Out std_logic;\r
171	SR_ERROR : Out std_logic;\r
a76e12bd	172	PAR_SER_IN : Out std_logic_vector (7 downto 0);\r
377c0242	173	SYNC_FLAG : Out std_logic_vector (7 downto 0) );\r
	174	end component;\r
	175	\r
	176	component PCI_TOP\r
	177	Port ( FLAG : In std_logic_vector (7 downto 0);\r
	178	INT_REG : In std_logic_vector (7 downto 0);\r
	179	PCI_CBEn : In std_logic_vector (3 downto 0);\r
	180	PCI_CLOCK : In std_logic;\r
	181	PCI_FRAMEn : In std_logic;\r
	182	PCI_IDSEL : In std_logic;\r
	183	PCI_IRDYn : In std_logic;\r
	184	PCI_RSTn : In std_logic;\r
	185	R_FIFO_Q : In std_logic_vector (7 downto 0);\r
	186	REVISON_ID : In std_logic_vector (7 downto 0);\r
	187	VENDOR_ID : In std_logic_vector (15 downto 0);\r
	188	PCI_AD : InOut std_logic_vector (31 downto 0);\r
	189	PCI_PAR : InOut std_logic;\r
	190	AD_REG : Out std_logic_vector (31 downto 0);\r
	191	DEVSELn : Out std_logic;\r
	192	FIFO_RDn : Out std_logic;\r
	193	PCI_DEVSELn : Out std_logic;\r
	194	PCI_PERRn : Out std_logic;\r
	195	PCI_SERRn : Out std_logic;\r
	196	PCI_STOPn : Out std_logic;\r
	197	PCI_TRDYn : Out std_logic;\r
	198	READ_SEL : Out std_logic_vector (1 downto 0);\r
	199	READ_XX1_0 : Out std_logic;\r
	200	READ_XX3_2 : Out std_logic;\r
	201	READ_XX5_4 : Out std_logic;\r
	202	READ_XX7_6 : Out std_logic;\r
	203	REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
	204	REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
	205	REG_OUT_XX7 : Out std_logic_vector (7 downto 0);\r
	206	TRDYn : Out std_logic;\r
	207	WRITE_XX1_0 : Out std_logic;\r
	208	WRITE_XX3_2 : Out std_logic;\r
	209	WRITE_XX5_4 : Out std_logic;\r
	210	WRITE_XX7_6 : Out std_logic );\r
	211	end component;\r
	212	\r
2825d08e	213	component fifo_generator_v3_2\r
	214	port (\r
	215	clk: IN std_logic;\r
	216	din: IN std_logic_VECTOR(7 downto 0);\r
	217	rd_en: IN std_logic;\r
	218	rst: IN std_logic;\r
	219	wr_en: IN std_logic;\r
	220	almost_empty: OUT std_logic;\r
	221	almost_full: OUT std_logic;\r
	222	dout: OUT std_logic_VECTOR(7 downto 0);\r
	223	empty: OUT std_logic;\r
	224	full: OUT std_logic;\r
	225	prog_full: OUT std_logic);\r
	226	end component;\r
	227	\r
1afff8d4	228	component icon\r
	229	port\r
	230	(\r
	231	control0 : out std_logic_vector(35 downto 0)\r
	232	);\r
	233	end component;\r
	234	\r
	235	component ila\r
	236	port\r
	237	(\r
	238	control : in std_logic_vector(35 downto 0);\r
	239	clk : in std_logic;\r
a76e12bd	240	data : in std_logic_vector(35 downto 0);\r
1afff8d4	241	trig0 : in std_logic_vector(7 downto 0)\r
	242	);\r
	243	end component;\r
	244	\r
	245	\r
377c0242	246	begin\r
257c0fc1	247	SERIAL_IN <= SERIAL_OUT;\r
257c0fc1	248	SPC_RDY_IN <= SPC_RDY_OUT;\r
bba7a6d5	249	LED_2 <= TAST_RESn;\r
	250	LED_3 <= TAST_SETn;\r
	251	LED_4 <= '0';\r
	252	LED_5 <= not watch;\r
	253	PCI_INTAn <= watch;\r
a76e12bd	254	trig0(7 downto 0) <= (0 => watch, others => '0');\r
a76e12bd	255	data(0) <= watch;\r
1afff8d4	256	\r
a76e12bd	257	data(1) <= R_EFn;\r
	258	data(2) <= R_HFn;\r
	259	data(3) <= R_FFn;\r
	260	data(4) <= R_FIFO_READn;\r
	261	data(5) <= R_FIFO_RESETn;\r
	262	data(6) <= R_FIFO_RTn;\r
	263	data(7) <= R_FIFO_WRITEn;\r
	264	data(8) <= S_EFn;\r
	265	data(9) <= S_HFn;\r
	266	data(10) <= S_FFn;\r
	267	data(11) <= S_FIFO_READn;\r
	268	data(12) <= S_FIFO_RESETn;\r
	269	data(13) <= S_FIFO_RTn;\r
	270	data(14) <= S_FIFO_WRITEn;\r
	271	data(15) <= SERIAL_IN;\r
	272	data(16) <= SPC_RDY_IN;\r
	273	data(17) <= SERIAL_OUT;\r
	274	data(18) <= SPC_RDY_OUT;\r
377c0242	275	\r
	276	I19 : MESS_1_TB\r
	277	Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
	278	PCI_IDSEL=>PCI_IDSEL,\r
	279	REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
	280	TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,\r
	281	TB_PCI_IDSEL=>TB_IDSEL );\r
	282	I18 : VEN_REV_ID\r
	283	Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
	284	VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );\r
	285	I16 : INTERRUPT\r
	286	Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),\r
	287	INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,\r
	288	INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,\r
	289	INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
	290	INT_RES(7 downto 0)=>AD_REG(7 downto 0),\r
	291	PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
	292	READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
	293	TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
	294	TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
bba7a6d5	295	INTAn=>INTAn, PCI_INTAn=>watch);\r
377c0242	296	I14 : FIFO_CONTROL\r
	297	Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
	298	FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r
	299	PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),\r
	300	R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,\r
	301	RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,\r
	302	S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
	303	S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,\r
	304	SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,\r
	305	WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
	306	R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
	307	R_FIFO_READn=>R_FIFO_READn,\r
	308	R_FIFO_RESETn=>R_FIFO_RESETn,\r
	309	R_FIFO_RETRANSMITn=>R_FIFO_RTn,\r
	310	R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,\r
	311	S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,\r
	312	S_FIFO_RESETn=>S_FIFO_RESETn,\r
	313	S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
	314	S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
	315	SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
a76e12bd	316	PAR_SER_IN(7 downto 0)=>data(26 downto 19),\r
377c0242	317	SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
	318	I1 : PCI_TOP\r
	319	Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
	320	INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
	321	PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
	322	PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
	323	PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
	324	PCI_RSTn=>PCI_RSTn,\r
	325	R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),\r
	326	REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
	327	VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
	328	PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
	329	PCI_PAR=>PCI_PAR,\r
	330	AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
	331	DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
	332	PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,\r
	333	PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,\r
	334	PCI_TRDYn=>PCI_TRDYn,\r
	335	READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
	336	READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
	337	READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,\r
	338	REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),\r
	339	REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
	340	REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
	341	TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,\r
	342	WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
	343	WRITE_XX7_6=>WRITE_XX7_6 );\r
	344	\r
2825d08e	345	receive_fifo : fifo_generator_v3_2\r
	346	port map (\r
	347	clk => PCI_CLOCK,\r
	348	din => R_FIFO_D_IN,\r
	349	rd_en => not R_FIFO_READn,\r
	350	rst => not R_FIFO_RESETn,\r
	351	wr_en => not R_FIFO_WRITEn,\r
	352	dout => R_FIFO_Q_OUT,\r
	353	empty => R_EFn,\r
	354	full => R_FFn,\r
	355	prog_full => R_HFn);\r
	356	\r
	357	send_fifo : fifo_generator_v3_2\r
	358	port map (\r
	359	clk => PCI_CLOCK,\r
	360	din => S_FIFO_D_IN,\r
	361	rd_en => not S_FIFO_READn,\r
	362	rst => not S_FIFO_RESETn,\r
	363	wr_en => not S_FIFO_WRITEn,\r
	364	dout => S_FIFO_Q_OUT,\r
	365	empty => S_EFn,\r
	366	full => S_FFn,\r
	367	prog_full => S_HFn);\r
1afff8d4	368	\r
	369	i_icon : icon\r
	370	port map\r
	371	(\r
	372	control0 => control0\r
	373	);\r
	374	\r
	375	i_ila : ila\r
	376	port map\r
	377	(\r
	378	control => control0,\r
	379	clk => PCI_CLOCK,\r
	380	data => data,\r
	381	trig0 => trig0\r
	382	);\r
377c0242	383	end SCHEMATIC;\r