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[raggedstone]
/
dhwk_old
/
source
/
sync.v
Commit
Line
Data
ebba63a9
1
module sync2 (clk, d, q);
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input clk;
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input d;
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output q;
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reg q;
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always @(posedge clk)
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begin
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q <= d;
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end
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endmodule
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