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disable unused chipscope inputs
[raggedstone] / xps / data / raggedstone.ucf
CommitLineData
7fb867f8 1############################################################################
2## This system.ucf file is generated by Base System Builder based on the
3## settings in the selected Xilinx Board Definition file. Please add other
4## user constraints to this file based on customer design specifications.
5############################################################################
6
7Net sys_clk_pin LOC=AA11 | IOSTANDARD = LVCMOS33;
8Net sys_rst_pin LOC=AA3 | IOSTANDARD = LVCMOS33 | PULLUP;
9## System level constraints
10Net sys_clk_pin TNM_NET = sys_clk_pin;
11TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps;
12Net sys_rst_pin TIG;
13
14## IO Devices constraints
15
16#### Module RS232 constraints
17
18Net fpga_0_RS232_req_to_send_pin LOC=N20;
19Net fpga_0_RS232_req_to_send_pin IOSTANDARD = LVCMOS33;
20Net fpga_0_RS232_RX_pin LOC=Y22;
21Net fpga_0_RS232_RX_pin IOSTANDARD = LVCMOS33;
22Net fpga_0_RS232_TX_pin LOC=R18;
23Net fpga_0_RS232_TX_pin IOSTANDARD = LVCMOS33;
24
25Net RS232foff LOC=T22 | IOSTANDARD = LVCMOS33;
26
27#Net LED_out<0> LOC=AB5 | IOSTANDARD = LVTTL;
28Net LED_out<1> LOC=AA5 | IOSTANDARD = LVTTL;
29Net LED_out<2> LOC=AA4 | IOSTANDARD = LVTTL;
30Net LED_out<3> LOC=AB4 | IOSTANDARD = LVTTL;
31
32Net SEVENSEG_out<12> LOC=AB20 | IOSTANDARD = LVTTL;
33Net SEVENSEG_out<11> LOC=AA20 | IOSTANDARD = LVTTL;
34Net SEVENSEG_out<10> LOC=V18 | IOSTANDARD = LVTTL;
35Net SEVENSEG_out<9> LOC=Y17 | IOSTANDARD = LVTTL;
36Net SEVENSEG_out<8> LOC=AB18 | IOSTANDARD = LVTTL;
37Net SEVENSEG_out<7> LOC=AA18 | IOSTANDARD = LVTTL;
38Net SEVENSEG_out<6> LOC=W18 | IOSTANDARD = LVTTL;
39Net SEVENSEG_out<5> LOC=W17 | IOSTANDARD = LVTTL;
40Net SEVENSEG_out<4> LOC=AA17 | IOSTANDARD = LVTTL;
41Net SEVENSEG_out<3> LOC=U17 | IOSTANDARD = LVTTL;
42Net SEVENSEG_out<2> LOC=U16 | IOSTANDARD = LVTTL;
43Net SEVENSEG_out<1> LOC=U14 | IOSTANDARD = LVTTL;
44Net SEVENSEG_out<0> LOC=V17 | IOSTANDARD = LVTTL;
45
46Net MEM_FLASH_DQ<0> LOC=AA10 | IOSTANDARD = LVCMOS33;
47Net MEM_FLASH_DQ<1> LOC=W11 | IOSTANDARD = LVCMOS33;
48Net MEM_FLASH_DQ<2> LOC=Y11 | IOSTANDARD = LVCMOS33;
49Net MEM_FLASH_DQ<3> LOC=U11 | IOSTANDARD = LVCMOS33;
50Net MEM_FLASH_DQ<4> LOC=W13 | IOSTANDARD = LVCMOS33;
51Net MEM_FLASH_DQ<5> LOC=V13 | IOSTANDARD = LVCMOS33;
52Net MEM_FLASH_DQ<6> LOC=Y13 | IOSTANDARD = LVCMOS33;
53Net MEM_FLASH_DQ<7> LOC=W14 | IOSTANDARD = LVCMOS33;
54
55Net MEM_FLASH_ADDR<0> LOC=Y10 | IOSTANDARD = LVCMOS33;
56Net MEM_FLASH_ADDR<1> LOC=W10 | IOSTANDARD = LVCMOS33;
57Net MEM_FLASH_ADDR<2> LOC=V10 | IOSTANDARD = LVCMOS33;
58Net MEM_FLASH_ADDR<3> LOC=W9 | IOSTANDARD = LVCMOS33;
59Net MEM_FLASH_ADDR<4> LOC=W8 | IOSTANDARD = LVCMOS33;
60Net MEM_FLASH_ADDR<5> LOC=AB8 | IOSTANDARD = LVCMOS33;
61Net MEM_FLASH_ADDR<6> LOC=AA8 | IOSTANDARD = LVCMOS33;
62Net MEM_FLASH_ADDR<7> LOC=AA9 | IOSTANDARD = LVCMOS33;
63Net MEM_FLASH_ADDR<8> LOC=V9 | IOSTANDARD = LVCMOS33;
64Net MEM_FLASH_ADDR<9> LOC=AA15 | IOSTANDARD = LVCMOS33;
65Net MEM_FLASH_ADDR<10> LOC=U12 | IOSTANDARD = LVCMOS33;
66Net MEM_FLASH_ADDR<11> LOC=AB15 | IOSTANDARD = LVCMOS33;
67Net MEM_FLASH_ADDR<12> LOC=AB9 | IOSTANDARD = LVCMOS33;
68Net MEM_FLASH_ADDR<13> LOC=AB14 | IOSTANDARD = LVCMOS33;
69Net MEM_FLASH_ADDR<14> LOC=AA13 | IOSTANDARD = LVCMOS33;
70Net MEM_FLASH_ADDR<15> LOC=AB10 | IOSTANDARD = LVCMOS33;
71Net MEM_FLASH_ADDR<16> LOC=AB11 | IOSTANDARD = LVCMOS33;
72Net MEM_FLASH_ADDR<17> LOC=AB13 | IOSTANDARD = LVCMOS33;
73Net MEM_FLASH_ADDR<18> LOC=Y12 | IOSTANDARD = LVCMOS33;
74
75Net DBG_FLASH_ADDR<31> LOC=Y1 | IOSTANDARD = LVCMOS33;
76Net DBG_FLASH_ADDR<30> LOC=U2 | IOSTANDARD = LVCMOS33;
77Net DBG_FLASH_ADDR<29> LOC=U3 | IOSTANDARD = LVCMOS33;
78Net DBG_FLASH_ADDR<28> LOC=T1 | IOSTANDARD = LVCMOS33;
79Net DBG_FLASH_ADDR<27> LOC=T2 | IOSTANDARD = LVCMOS33;
80Net DBG_FLASH_ADDR<26> LOC=M6 | IOSTANDARD = LVCMOS33;
81Net DBG_FLASH_ADDR<25> LOC=M5 | IOSTANDARD = LVCMOS33;
82Net DBG_FLASH_ADDR<24> LOC=M1 | IOSTANDARD = LVCMOS33;
83Net DBG_FLASH_ADDR<23> LOC=M2 | IOSTANDARD = LVCMOS33;
84Net DBG_FLASH_ADDR<22> LOC=L5 | IOSTANDARD = LVCMOS33;
85Net DBG_FLASH_ADDR<21> LOC=L6 | IOSTANDARD = LVCMOS33;
86Net DBG_FLASH_ADDR<20> LOC=K1 | IOSTANDARD = LVCMOS33;
87Net DBG_FLASH_ADDR<19> LOC=K2 | IOSTANDARD = LVCMOS33;
88Net DBG_FLASH_ADDR<18> LOC=F4 | IOSTANDARD = LVCMOS33;
89Net DBG_FLASH_ADDR<17> LOC=E3 | IOSTANDARD = LVCMOS33;
90Net DBG_FLASH_ADDR<16> LOC=F2 | IOSTANDARD = LVCMOS33;
91Net DBG_FLASH_ADDR<15> LOC=F3 | IOSTANDARD = LVCMOS33;
92Net DBG_FLASH_ADDR<14> LOC=E2 | IOSTANDARD = LVCMOS33;
93Net DBG_FLASH_ADDR<13> LOC=E1 | IOSTANDARD = LVCMOS33;
94Net DBG_FLASH_ADDR<12> LOC=W1 | IOSTANDARD = LVCMOS33;
95Net DBG_FLASH_ADDR<11> LOC=W2 | IOSTANDARD = LVCMOS33;
96Net DBG_FLASH_ADDR<10> LOC=V5 | IOSTANDARD = LVCMOS33;
97Net DBG_FLASH_ADDR<9> LOC=U5 | IOSTANDARD = LVCMOS33;
98Net DBG_FLASH_ADDR<8> LOC=V2 | IOSTANDARD = LVCMOS33;
99Net DBG_FLASH_ADDR<7> LOC=V1 | IOSTANDARD = LVCMOS33;
100Net DBG_FLASH_ADDR<6> LOC=U4 | IOSTANDARD = LVCMOS33;
101Net DBG_FLASH_ADDR<5> LOC=T4 | IOSTANDARD = LVCMOS33;
102Net DBG_FLASH_ADDR<4> LOC=T5 | IOSTANDARD = LVCMOS33;
103Net DBG_FLASH_ADDR<3> LOC=T6 | IOSTANDARD = LVCMOS33;
104Net DBG_FLASH_ADDR<2> LOC=M4 | IOSTANDARD = LVCMOS33;
105Net DBG_FLASH_ADDR<1> LOC=M3 | IOSTANDARD = LVCMOS33;
106Net DBG_FLASH_ADDR<0> LOC=L3 | IOSTANDARD = LVCMOS33;
107
108Net MEM_FLASH_CE<0> LOC=V14 | IOSTANDARD = LVCMOS33;
109Net MEM_FLASH_OE<0> LOC=U13 | IOSTANDARD = LVCMOS33;
110Net MEM_FLASH_WE LOC=W12 | IOSTANDARD = LVCMOS33;
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