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1 | library ieee;\r |
| 2 | use ieee.std_logic_1164.all;\r |
| 3 | use ieee.std_logic_arith.all;\r |
| 4 | use ieee.std_logic_unsigned.all;\r |
| 5 | \r |
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6 | entity dhwk is\r |
| 7 | port (\r |
| 8 | \r |
| 9 | -- General \r |
| 10 | PCI_CLK : in std_logic;\r |
| 11 | PCI_nRES : in std_logic;\r |
| 12 | \r |
| 13 | -- PCI target 32bits\r |
| 14 | PCI_AD : inout std_logic_vector(31 downto 0);\r |
| 15 | PCI_CBE : in std_logic_vector(3 downto 0);\r |
| 16 | PCI_PAR : out std_logic; \r |
| 17 | PCI_nFRAME : in std_logic;\r |
| 18 | PCI_nIRDY : in std_logic;\r |
| 19 | PCI_nTRDY : out std_logic;\r |
| 20 | PCI_nDEVSEL : out std_logic;\r |
| 21 | PCI_nSTOP : out std_logic;\r |
| 22 | PCI_IDSEL : in std_logic;\r |
| 23 | PCI_nPERR : out std_logic;\r |
| 24 | PCI_nSERR : out std_logic;\r |
| 25 | PCI_nINT : out std_logic;\r |
| 26 | \r |
| 27 | -- debug signals\r |
| 28 | LED3 : out std_logic;\r |
| 29 | LED2 : out std_logic;\r |
| 30 | LED4 : out std_logic;\r |
| 31 | LED5 : out std_logic\r |
| 32 | \r |
| 33 | );\r |
| 34 | end dhwk;\r |
| 35 | \r |
| 36 | \r |
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37 | architecture dhwk_arch of dhwk is\r |
| 38 | \r |
| 39 | \r |
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40 | component pci32tlite\r |
| 41 | port (\r |
| 42 | \r |
| 43 | -- General \r |
| 44 | clk33 : in std_logic;\r |
| 45 | nrst : in std_logic;\r |
| 46 | \r |
| 47 | -- PCI target 32bits\r |
| 48 | ad : inout std_logic_vector(31 downto 0);\r |
| 49 | cbe : in std_logic_vector(3 downto 0);\r |
| 50 | par : out std_logic; \r |
| 51 | frame : in std_logic;\r |
| 52 | irdy : in std_logic;\r |
| 53 | trdy : out std_logic;\r |
| 54 | devsel : out std_logic;\r |
| 55 | stop : out std_logic;\r |
| 56 | idsel : in std_logic;\r |
| 57 | perr : out std_logic;\r |
| 58 | serr : out std_logic;\r |
| 59 | intb : out std_logic;\r |
| 60 | \r |
| 61 | -- Master whisbone\r |
| 62 | wb_adr_o : out std_logic_vector(24 downto 1); \r |
| 63 | wb_dat_i : in std_logic_vector(15 downto 0);\r |
| 64 | wb_dat_o : out std_logic_vector(15 downto 0);\r |
| 65 | wb_sel_o : out std_logic_vector(1 downto 0);\r |
| 66 | wb_we_o : out std_logic;\r |
| 67 | wb_stb_o : out std_logic;\r |
| 68 | wb_cyc_o : out std_logic;\r |
| 69 | wb_ack_i : in std_logic;\r |
| 70 | wb_err_i : in std_logic;\r |
| 71 | wb_int_i : in std_logic;\r |
| 72 | \r |
| 73 | -- debug signals\r |
| 74 | debug_init : out std_logic;\r |
| 75 | debug_access : out std_logic \r |
| 76 | \r |
| 77 | );\r |
| 78 | end component;\r |
| 79 | \r |
| 80 | component heartbeat\r |
| 81 | port (\r |
| 82 | clk_i : in std_logic;\r |
| 83 | nrst_i : in std_logic;\r |
| 84 | led2_o : out std_logic;\r |
| 85 | led3_o : out std_logic;\r |
| 86 | led4_o : out std_logic;\r |
| 87 | led5_o : out std_logic\r |
| 88 | );\r |
| 89 | end component;\r |
| 90 | \r |
| 7b50ad38 |
91 | component generic_fifo_sc_a\r |
| 92 | port (\r |
| 93 | clk : in std_logic;\r |
| 94 | rst : in std_logic;\r |
| 95 | clr : in std_logic;\r |
| 96 | din : in std_logic_vector(7 downto 0);\r |
| 97 | we : in std_logic;\r |
| 98 | dout : out std_logic_vector(7 downto 0);\r |
| 99 | re : in std_logic;\r |
| 100 | full : out std_logic;\r |
| 101 | full_r : out std_logic;\r |
| 102 | empty : out std_logic;\r |
| 103 | empty_r : out std_logic;\r |
| 104 | full_n : out std_logic;\r |
| 105 | full_n_r : out std_logic;\r |
| 106 | empty_n : out std_logic;\r |
| 107 | empty_n_r : out std_logic;\r |
| 108 | level : out std_logic_vector(1 downto 0)\r |
| 109 | );\r |
| 110 | end component;\r |
| 111 | \r |
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112 | component generic_dpram\r |
| 113 | port (\r |
| 114 | rclk : in std_logic;\r |
| 115 | rrst : in std_logic;\r |
| 116 | rce : in std_logic;\r |
| 117 | oe : in std_logic;\r |
| 118 | raddr : in std_logic_vector(11 downto 0);\r |
| 119 | do : out std_logic_vector(7 downto 0);\r |
| 120 | wclk : in std_logic;\r |
| 121 | wrst : in std_logic;\r |
| 122 | wce : in std_logic;\r |
| 123 | we : in std_logic;\r |
| 124 | waddr : in std_logic_vector(11 downto 0);\r |
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125 | di : in std_logic_vector(7 downto 0)\r |
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126 | );\r |
| 127 | end component;\r |
| 128 | \r |
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129 | \r |
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130 | signal wb_adr : std_logic_vector(24 downto 1); \r |
| 131 | signal wb_dat_out : std_logic_vector(15 downto 0);\r |
| 132 | signal wb_dat_in : std_logic_vector(15 downto 0);\r |
| 133 | signal wb_sel : std_logic_vector(1 downto 0);\r |
| 134 | signal wb_we : std_logic;\r |
| 135 | signal wb_stb : std_logic;\r |
| 136 | signal wb_cyc : std_logic;\r |
| 137 | signal wb_ack : std_logic;\r |
| 138 | signal wb_err : std_logic;\r |
| 139 | signal wb_int : std_logic;\r |
| 140 | \r |
| 141 | \r |
| 142 | begin\r |
| 143 | \r |
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144 | u_pci: component pci32tlite\r |
| 145 | port map(\r |
| 146 | clk33 => PCI_CLK,\r |
| 147 | nrst => PCI_nRES,\r |
| 148 | ad => PCI_AD,\r |
| 149 | cbe => PCI_CBE,\r |
| 150 | par => PCI_PAR,\r |
| 151 | frame => PCI_nFRAME,\r |
| 152 | irdy => PCI_nIRDY,\r |
| 153 | trdy => PCI_nTRDY,\r |
| 154 | devsel => PCI_nDEVSEL,\r |
| 155 | stop => PCI_nSTOP,\r |
| 156 | idsel => PCI_IDSEL,\r |
| 157 | perr => PCI_nPERR,\r |
| 158 | serr => PCI_nSERR,\r |
| 159 | intb => PCI_nINT,\r |
| 160 | wb_adr_o => wb_adr, \r |
| 161 | wb_dat_i => wb_dat_out,\r |
| 162 | wb_dat_o => wb_dat_in,\r |
| 163 | wb_sel_o => wb_sel, \r |
| 164 | wb_we_o => wb_we,\r |
| 165 | wb_stb_o => wb_stb, \r |
| 166 | wb_cyc_o => wb_cyc,\r |
| 167 | wb_ack_i => wb_ack,\r |
| 168 | wb_err_i => wb_err,\r |
| 169 | wb_int_i => wb_int\r |
| 170 | -- debug_init => LED3,\r |
| 171 | -- debug_access => LED2\r |
| 172 | );\r |
| 173 | \r |
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174 | my_heartbeat: component heartbeat\r |
| 175 | port map( \r |
| 176 | clk_i => PCI_CLK,\r |
| 177 | nrst_i => PCI_nRES,\r |
| 178 | led2_o => LED2,\r |
| 179 | led3_o => LED3,\r |
| 180 | led4_o => LED4,\r |
| 181 | led5_o => LED5\r |
| 182 | );\r |
| 183 | \r |
| 184 | end dhwk_arch;\r |
projects / raggedstone / blame