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[raggedstone] / dhwk / source / CONT_FSM.vhd

-- J.STELZNER\r
-- INFORMATIK-3 LABOR\r
-- 23.08.2006\r
-- File: CONT_FSM.VHD\r
\r
library ieee;\r
use ieee.std_logic_1164.all ;\r
\r
entity CONT_FSM is\r
	port\r
	(\r
	PCI_CLOCK		:in		std_logic; \r
	PCI_RSTn		:in		std_logic; \r
	IO_READ			:in		std_logic;\r
	IO_WRITE		:in		std_logic;\r
	CONF_READ		:in		std_logic;\r
	CONF_WRITE	:in		std_logic;\r
	FIFO_READ		:in		std_logic;\r
	READ				:out	std_logic;--> MUX_SEL(1) , OE_PCI_AD \r
 	PERR_CHECK	:out	std_logic;		\r
	DEVSELn			:out	std_logic;\r
	OE_PCI_PAR	:out	std_logic;\r
	OE_PCI_PERR	:out	std_logic;\r
	TRDYn				:out	std_logic;\r
	PCI_TRDYn		:out	std_logic;	--	s/t/s\r
	PCI_STOPn		:out	std_logic;	--	s/t/s	\r
	PCI_DEVSELn	:out	std_logic;	--	s/t/s	\r
	FIFO_RDn		:out	std_logic\r
	);\r
end entity CONT_FSM ;\r
\r
architecture CONT_FSM_DESIGN of CONT_FSM is\r
\r
\r
\r
--**********************************************************\r
--***              CONTROL FSM CODIERUNG                 ***\r
--**********************************************************\r
--\r
--\r
--\r
--                                                           |----------- HELP\r
--                                                           ||---------- FIFO_READn\r
--                                                           |||--------- OE_PCI_PERR  	\r
--              	           				        	          		 ||||-------- PERR_CHECK  \r
--              	           				    	    	     				 |||||------- TRDYn   \r
--              	        	   				    	         			   ||||||------ STOPn                                                    \r
--              	    	      					             				 |||||||----- DEVSELn   \r
--                  			    	    	               			   ||||||||---- OE_PCI_PAR   \r
--																  												 |||||||||--- OE_CONTROL   \r
--																												   ||||||||||-- READ / MUX_SEL(1) / OE_PCI_AD \r
--																 													 ||||||||||		  \r
	constant	ST_IDLE	:std_logic_vector (9 downto 0) := "0100111000" ;-- 138\r
\r
	constant	ST_READ_1			:std_logic_vector (9 downto 0) := "0100110011" ;-- 133\r
	constant	ST_READ_2			:std_logic_vector (9 downto 0) := "0100000111" ;-- 107\r
	constant	ST_READ_3			:std_logic_vector (9 downto 0) := "0100111111" ;-- 13F\r
\r
	constant	ST_RD_FIFO_1	:std_logic_vector (9 downto 0) := "0000110011" ;-- 033\r
	constant	ST_RD_FIFO_2	:std_logic_vector (9 downto 0) := "1000110011" ;-- 233\r
\r
\r
	constant	ST_WRITE_1		:std_logic_vector (9 downto 0) := "0111110010" ;-- 1F2\r
	constant	ST_WRITE_2		:std_logic_vector (9 downto 0) := "0110000010" ;-- 182\r
	constant	ST_WRITE_3		:std_logic_vector (9 downto 0) := "0110111010" ;-- 1BA\r
\r
	signal		CONTROL_STATE	:std_logic_vector (9 downto 0);\r
\r
\r
--signal		DEVSELn			:std_logic;\r
	signal		STOPn			:std_logic;\r
--signal		TRDYn			:std_logic;\r
\r
--************************************************************\r
--***             FSM SPEICHER-AUTOMAT                     ***\r
--************************************************************\r
\r
	attribute syn_state_machine : boolean;\r
	attribute syn_state_machine of CONTROL_STATE : signal is false;\r
\r
begin\r
\r
--**********************************************************\r
--***                  CONTROL FSM                       ***\r
--**********************************************************\r
\r
	process (PCI_CLOCK, PCI_RSTn) \r
	begin\r
		if	PCI_RSTn = '0'	then	CONTROL_STATE	<= ST_IDLE;\r
\r
		elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
 \r
			case CONTROL_STATE is\r
	\r
				when ST_IDLE => \r
					if			IO_READ		= '1' then\r
															CONTROL_STATE <= ST_READ_1;\r
\r
	  		  	elsif	CONF_READ	= '1' then\r
															CONTROL_STATE <= ST_READ_1; \r
\r
						elsif	IO_WRITE	= '1' then\r
															CONTROL_STATE <= ST_WRITE_1;   \r
  \r
			    	elsif	CONF_WRITE	= '1' then\r
															CONTROL_STATE <= ST_WRITE_1;\r
     \r
   		    	else    					CONTROL_STATE <= ST_IDLE;\r
					end if;	\r
\r
--			when	ST_READ_1		=>	CONTROL_STATE	<=	ST_READ_2;\r
				when	ST_READ_1		=>	\r
					if			FIFO_READ	= '1' then\r
															CONTROL_STATE <= ST_RD_FIFO_1;\r
						else    					CONTROL_STATE <= ST_READ_2;\r
					end if;	\r
\r
\r
				when	ST_READ_2		=>	CONTROL_STATE	<=	ST_READ_3;\r
				when	ST_READ_3		=>	CONTROL_STATE	<=	ST_IDLE;\r
\r
				when	ST_RD_FIFO_1=>	CONTROL_STATE	<=	ST_RD_FIFO_2;\r
				when	ST_RD_FIFO_2=>	CONTROL_STATE	<=	ST_READ_2;\r
\r
\r
	 \r
				when	ST_WRITE_1	=>	CONTROL_STATE	<=	ST_WRITE_2;\r
				when	ST_WRITE_2	=>	CONTROL_STATE	<=	ST_WRITE_3;\r
				when	ST_WRITE_3	=> 	CONTROL_STATE	<=	ST_IDLE;\r
\r
		\r
				when others				=>	CONTROL_STATE	<=	ST_IDLE; \r
\r
 			end case;		-- COMM_STATE    \r
		end if;				-- CLOCK   \r
	end process;			-- PROCESS\r
\r
\r
	READ				<=	CONTROL_STATE(0);\r
--OE_CONTROL	<=	CONTROL_STATE(1);\r
	OE_PCI_PAR	<=	CONTROL_STATE(2);\r
	DEVSELn			<=	CONTROL_STATE(3);\r
	STOPn				<= 	CONTROL_STATE(4);\r
	TRDYn				<=	CONTROL_STATE(5);\r
	PERR_CHECK	<=	CONTROL_STATE(6);\r
	OE_PCI_PERR	<=	CONTROL_STATE(7);\r
\r
	FIFO_RDn		<=	CONTROL_STATE(8);\r
\r
\r
	PCI_DEVSELn	<=	CONTROL_STATE(3)	when	CONTROL_STATE(1) = '1' else 'Z';\r
	PCI_STOPn 	<=	STOPn     				when	CONTROL_STATE(1) = '1' else 'Z';		                                                      \r
	PCI_TRDYn	  <=	CONTROL_STATE(5)	when	CONTROL_STATE(1) = '1' else 'Z';	\r
\r
end architecture CONT_FSM_DESIGN ;\r
\r