]> cvs.zerfleddert.de Git - raggedstone/blame - dhwk/source/MESS_1_TB.vhd
chipscope
[raggedstone] / dhwk / source / MESS_1_TB.vhd
CommitLineData
377c0242 1-- J.STELZNER\r
2-- INFORMATIK-3 LABOR\r
3-- 29.08.2006\r
4-- File: MESS_1_TB.VHD\r
5\r
6library IEEE;\r
7use IEEE.std_logic_1164.all;\r
8\r
9entity MESS_1_TB is\r
10 port\r
11 (\r
12 KONST_1 :in std_logic;\r
13 PCI_IDSEL :in std_logic;\r
14 DEVSELn :in std_logic;\r
15 INTAn :in std_logic;\r
16 REG_OUT_XX7 :in std_logic_vector(7 downto 0);\r
17 TB_PCI_IDSEL :out std_logic;\r
18 TB_DEVSELn :out std_logic;\r
19 TB_INTAn :out std_logic\r
20 );\r
21end entity MESS_1_TB;\r
22\r
23architecture MESS_1_TB_DESIGN of MESS_1_TB is\r
24 \r
25begin\r
26\r
27 TB_PCI_IDSEL <= PCI_IDSEL and KONST_1;\r
28\r
29 TB_INTAn <= INTAn and KONST_1; \r
30 \r
31 TB_DEVSELn <= DEVSELn when REG_OUT_XX7(7) = '0' else (not REG_OUT_XX7(6));\r
32\r
33end architecture MESS_1_TB_DESIGN;\r
Impressum, Datenschutz