[raggedstone] / dhwk / source / Parity_4.vhd

-- J.STELZNER\r
-- INFORMATIK-3 LABOR\r
-- 23.08.2006\r
-- File: PARITY_4.VHD\r
\r
library ieee;\r
use ieee.std_logic_1164.all;\r
\r
entity PARITY_4 is\r
	port\r
	(\r
	PAR_IN	:in		std_logic_vector(3 downto 0);	\r
	PAR_OUT	:out	std_logic\r
	);\r
end entity PARITY_4 ; \r
\r
architecture PARITY_4_DESIGN of PARITY_4 is\r
\r
begin\r
\r
	PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) ;\r
\r
end architecture PARITY_4_DESIGN;\r
Commit	Line	Data
377c0242	1	-- J.STELZNER\r
	2	-- INFORMATIK-3 LABOR\r
	3	-- 23.08.2006\r
	4	-- File: PARITY_4.VHD\r
	5	\r
	6	library ieee;\r
	7	use ieee.std_logic_1164.all;\r
	8	\r
	9	entity PARITY_4 is\r
	10	port\r
	11	(\r
	12	PAR_IN :in std_logic_vector(3 downto 0); \r
	13	PAR_OUT :out std_logic\r
	14	);\r
	15	end entity PARITY_4 ; \r
	16	\r
	17	architecture PARITY_4_DESIGN of PARITY_4 is\r
	18	\r
	19	begin\r
	20	\r
	21	PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) ;\r
	22	\r
	23	end architecture PARITY_4_DESIGN;\r