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377c0242 1-- J.STELZNER\r
2-- INFORMATIK-3 LABOR\r
3-- 23.08.2006\r
4-- File: PARITY_4.VHD\r
5\r
6library ieee;\r
7use ieee.std_logic_1164.all;\r
8\r
9entity PARITY_4 is\r
10 port\r
11 (\r
12 PAR_IN :in std_logic_vector(3 downto 0); \r
13 PAR_OUT :out std_logic\r
14 );\r
15end entity PARITY_4 ; \r
16\r
17architecture PARITY_4_DESIGN of PARITY_4 is\r
18\r
19begin\r
20\r
21 PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) ;\r
22\r
23end architecture PARITY_4_DESIGN;\r
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