[raggedstone] / dhwk / source / fifo_control.vhd

-- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007\r
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LIBRARY ieee;\r
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USE ieee.std_logic_1164.ALL;\r
USE ieee.numeric_std.ALL;\r
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\r
entity FIFO_CONTROL is\r
      Port ( FIFO_RDn : In    std_logic;\r
             FLAG_IN_0 : In    std_logic;\r
             FLAG_IN_4 : In    std_logic;\r
                HOLD : In    std_logic;\r
             KONST_1 : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
             PSC_ENABLE : In    std_logic;\r
               R_EFn : In    std_logic;\r
               R_FFn : In    std_logic;\r
               R_HFn : In    std_logic;\r
               RESET : In    std_logic;\r
               S_EFn : In    std_logic;\r
               S_FFn : In    std_logic;\r
             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
               S_HFn : In    std_logic;\r
             SERIAL_IN : In    std_logic;\r
             SPC_ENABLE : In    std_logic;\r
             SPC_RDY_IN : In    std_logic;\r
             WRITE_XX1_0 : In    std_logic;\r
             R_ERROR : Out   std_logic;\r
             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
             R_FIFO_READn : Out   std_logic;\r
             R_FIFO_RESETn : Out   std_logic;\r
             R_FIFO_RETRANSMITn : Out   std_logic;\r
             R_FIFO_WRITEn : Out   std_logic;\r
             RESERVE : Out   std_logic;\r
             S_ERROR : Out   std_logic;\r
             S_FIFO_READn : Out   std_logic;\r
             S_FIFO_RESETn : Out   std_logic;\r
             S_FIFO_RETRANSMITn : Out   std_logic;\r
             S_FIFO_WRITEn : Out   std_logic;\r
             SERIAL_OUT : Out   std_logic;\r
             SPC_RDY_OUT : Out   std_logic;\r
             SR_ERROR : Out   std_logic;\r
             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
end FIFO_CONTROL;\r
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architecture SCHEMATIC of FIFO_CONTROL is\r
\r
   SIGNAL gnd : std_logic := '0';\r
   SIGNAL vcc : std_logic := '1';\r
\r
   signal XXXR_FIFO_WRITEn : std_logic;\r
   signal XXXS_FIFO_READn : std_logic;\r
   signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);\r
   signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);\r
\r
   component SER_PAR_CON\r
      Port ( PCI_CLOCK : In    std_logic;\r
               RESET : In    std_logic;\r
             SERIAL_IN : In    std_logic;\r
             SPC_ENABLE : In    std_logic;\r
             SYNC_R_FIFO_FFn : In    std_logic;\r
             PAR_OUT : Out   std_logic_vector (7 downto 0);\r
             R_FIFO_WRITEn : Out   std_logic;\r
             SPC_RDY_OUT : Out   std_logic );\r
   end component;\r
\r
   component PAR_SER_CON\r
      Port (  PAR_IN : In    std_logic_vector (7 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
             PSC_ENABLE : In    std_logic;\r
               RESET : In    std_logic;\r
             SPC_RDY_IN : In    std_logic;\r
             SYNC_S_FIFO_EFn : In    std_logic;\r
             S_FIFO_READn : Out   std_logic;\r
             SER_OUT : Out   std_logic );\r
   end component;\r
\r
   component FIFO_IO_CONTROL\r
      Port ( FIFO_RDn : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
               RESET : In    std_logic;\r
             SYNC_FLAG_1 : In    std_logic;\r
             SYNC_FLAG_7 : In    std_logic;\r
             WRITE_XX1_0 : In    std_logic;\r
             R_ERROR : Out   std_logic;\r
             R_FIFO_READn : Out   std_logic;\r
             R_FIFO_RESETn : Out   std_logic;\r
             R_FIFO_RETRANSMITn : Out   std_logic;\r
             S_ERROR : Out   std_logic;\r
             S_FIFO_RESETn : Out   std_logic;\r
             S_FIFO_RETRANSMITn : Out   std_logic;\r
             S_FIFO_WRITEn : Out   std_logic;\r
             SR_ERROR : Out   std_logic );\r
   end component;\r
\r
   component CONNECTING_FSM\r
      Port ( PCI_CLOCK : In    std_logic;\r
             PSC_ENABLE : In    std_logic;\r
               RESET : In    std_logic;\r
             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
             SPC_ENABLE : In    std_logic;\r
             SYNC_R_FIFO_FFn : In    std_logic;\r
             SYNC_S_FIFO_EFn : In    std_logic;\r
             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
             R_FIFO_WRITEn : Out   std_logic;\r
             S_FIFO_READn : Out   std_logic );\r
   end component;\r
\r
   component FLAG_BUS\r
      Port ( FLAG_IN_0 : In    std_logic;\r
             FLAG_IN_4 : In    std_logic;\r
                HOLD : In    std_logic;\r
              KONS_1 : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
               R_EFn : In    std_logic;\r
               R_FFn : In    std_logic;\r
               R_HFn : In    std_logic;\r
               S_EFn : In    std_logic;\r
               S_FFn : In    std_logic;\r
               S_HFn : In    std_logic;\r
             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
   end component;\r
\r
begin\r
\r
   SYNC_FLAG <= SYNC_FLAG_DUMMY;\r
\r
   RESERVE <= gnd;\r
   I23 : SER_PAR_CON\r
      Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
                 SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,\r
                 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
                 PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
                 R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );\r
   I22 : PAR_SER_CON\r
      Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
                 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
                 RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,\r
                 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
                 S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );\r
   I21 : FIFO_IO_CONTROL\r
      Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
                 SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),\r
                 SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),\r
                 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
                 R_FIFO_READn=>R_FIFO_READn,\r
                 R_FIFO_RESETn=>R_FIFO_RESETn,\r
                 R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,\r
                 S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,\r
                 S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,\r
                 S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );\r
   I20 : CONNECTING_FSM\r
      Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
                 RESET=>RESET,\r
                 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
                 SPC_ENABLE=>SPC_ENABLE,\r
                 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
                 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
                 R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),\r
                 R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,\r
                 S_FIFO_READn=>XXXS_FIFO_READn );\r
   I19 : FLAG_BUS\r
      Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,\r
                 KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,\r
                 R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,\r
                 S_HFn=>S_HFn,\r
                 SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );\r
\r
end SCHEMATIC;\r
Commit	Line	Data
377c0242	1	-- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007\r
	2	\r
	3	\r
	4	\r
	5	LIBRARY ieee;\r
	6	\r
	7	USE ieee.std_logic_1164.ALL;\r
	8	USE ieee.numeric_std.ALL;\r
	9	\r
	10	\r
	11	entity FIFO_CONTROL is\r
	12	Port ( FIFO_RDn : In std_logic;\r
	13	FLAG_IN_0 : In std_logic;\r
	14	FLAG_IN_4 : In std_logic;\r
	15	HOLD : In std_logic;\r
	16	KONST_1 : In std_logic;\r
	17	PCI_CLOCK : In std_logic;\r
	18	PSC_ENABLE : In std_logic;\r
	19	R_EFn : In std_logic;\r
	20	R_FFn : In std_logic;\r
	21	R_HFn : In std_logic;\r
	22	RESET : In std_logic;\r
	23	S_EFn : In std_logic;\r
	24	S_FFn : In std_logic;\r
	25	S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
	26	S_HFn : In std_logic;\r
	27	SERIAL_IN : In std_logic;\r
	28	SPC_ENABLE : In std_logic;\r
	29	SPC_RDY_IN : In std_logic;\r
	30	WRITE_XX1_0 : In std_logic;\r
	31	R_ERROR : Out std_logic;\r
	32	R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
	33	R_FIFO_READn : Out std_logic;\r
	34	R_FIFO_RESETn : Out std_logic;\r
	35	R_FIFO_RETRANSMITn : Out std_logic;\r
	36	R_FIFO_WRITEn : Out std_logic;\r
	37	RESERVE : Out std_logic;\r
	38	S_ERROR : Out std_logic;\r
	39	S_FIFO_READn : Out std_logic;\r
	40	S_FIFO_RESETn : Out std_logic;\r
	41	S_FIFO_RETRANSMITn : Out std_logic;\r
	42	S_FIFO_WRITEn : Out std_logic;\r
	43	SERIAL_OUT : Out std_logic;\r
	44	SPC_RDY_OUT : Out std_logic;\r
	45	SR_ERROR : Out std_logic;\r
	46	SYNC_FLAG : Out std_logic_vector (7 downto 0) );\r
	47	end FIFO_CONTROL;\r
	48	\r
	49	architecture SCHEMATIC of FIFO_CONTROL is\r
	50	\r
	51	SIGNAL gnd : std_logic := '0';\r
	52	SIGNAL vcc : std_logic := '1';\r
	53	\r
	54	signal XXXR_FIFO_WRITEn : std_logic;\r
	55	signal XXXS_FIFO_READn : std_logic;\r
	56	signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);\r
	57	signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);\r
	58	\r
	59	component SER_PAR_CON\r
	60	Port ( PCI_CLOCK : In std_logic;\r
	61	RESET : In std_logic;\r
	62	SERIAL_IN : In std_logic;\r
	63	SPC_ENABLE : In std_logic;\r
	64	SYNC_R_FIFO_FFn : In std_logic;\r
65	PAR_OUT : Out std_logic_vector (7 downto 0);\r
66	R_FIFO_WRITEn : Out std_logic;\r
67	SPC_RDY_OUT : Out std_logic );\r
68	end component;\r
69	\r
70	component PAR_SER_CON\r
71	Port ( PAR_IN : In std_logic_vector (7 downto 0);\r
72	PCI_CLOCK : In std_logic;\r
73	PSC_ENABLE : In std_logic;\r
74	RESET : In std_logic;\r
75	SPC_RDY_IN : In std_logic;\r
76	SYNC_S_FIFO_EFn : In std_logic;\r
77	S_FIFO_READn : Out std_logic;\r
78	SER_OUT : Out std_logic );\r
79	end component;\r
80	\r
81	component FIFO_IO_CONTROL\r
82	Port ( FIFO_RDn : In std_logic;\r
83	PCI_CLOCK : In std_logic;\r
84	RESET : In std_logic;\r
85	SYNC_FLAG_1 : In std_logic;\r
86	SYNC_FLAG_7 : In std_logic;\r
87	WRITE_XX1_0 : In std_logic;\r
88	R_ERROR : Out std_logic;\r
89	R_FIFO_READn : Out std_logic;\r
90	R_FIFO_RESETn : Out std_logic;\r
91	R_FIFO_RETRANSMITn : Out std_logic;\r
92	S_ERROR : Out std_logic;\r
93	S_FIFO_RESETn : Out std_logic;\r
94	S_FIFO_RETRANSMITn : Out std_logic;\r
95	S_FIFO_WRITEn : Out std_logic;\r
96	SR_ERROR : Out std_logic );\r
97	end component;\r
98	\r
99	component CONNECTING_FSM\r
100	Port ( PCI_CLOCK : In std_logic;\r
101	PSC_ENABLE : In std_logic;\r
102	RESET : In std_logic;\r
103	S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
104	SPC_ENABLE : In std_logic;\r
105	SYNC_R_FIFO_FFn : In std_logic;\r
106	SYNC_S_FIFO_EFn : In std_logic;\r
107	R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
108	R_FIFO_WRITEn : Out std_logic;\r
109	S_FIFO_READn : Out std_logic );\r
110	end component;\r
111	\r
112	component FLAG_BUS\r
113	Port ( FLAG_IN_0 : In std_logic;\r
114	FLAG_IN_4 : In std_logic;\r
115	HOLD : In std_logic;\r
116	KONS_1 : In std_logic;\r
117	PCI_CLOCK : In std_logic;\r
118	R_EFn : In std_logic;\r
119	R_FFn : In std_logic;\r
120	R_HFn : In std_logic;\r
121	S_EFn : In std_logic;\r
122	S_FFn : In std_logic;\r
123	S_HFn : In std_logic;\r
124	SYNC_FLAG : Out std_logic_vector (7 downto 0) );\r
125	end component;\r
126	\r
127	begin\r
128	\r
129	SYNC_FLAG <= SYNC_FLAG_DUMMY;\r
130	\r
131	RESERVE <= gnd;\r
132	I23 : SER_PAR_CON\r
133	Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
134	SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,\r
135	SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
136	PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
137	R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );\r
138	I22 : PAR_SER_CON\r
139	Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
140	PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
141	RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,\r
142	SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
143	S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );\r
144	I21 : FIFO_IO_CONTROL\r
145	Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
146	SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),\r
147	SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),\r
148	WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
149	R_FIFO_READn=>R_FIFO_READn,\r
150	R_FIFO_RESETn=>R_FIFO_RESETn,\r
151	R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,\r
152	S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,\r
153	S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,\r
154	S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );\r
155	I20 : CONNECTING_FSM\r
156	Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
157	RESET=>RESET,\r
158	S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
159	SPC_ENABLE=>SPC_ENABLE,\r
160	SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
161	SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
162	R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),\r
163	R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,\r
164	S_FIFO_READn=>XXXS_FIFO_READn );\r
165	I19 : FLAG_BUS\r
166	Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,\r
167	KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,\r
168	R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,\r
169	S_HFn=>S_HFn,\r
170	SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );\r
171	\r
172	end SCHEMATIC;\r