[raggedstone] / dhwk / source / user_io.vhd

-- VHDL model created from schematic user_io.sch -- Jan 09 09:34:12 2007\r
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\r
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LIBRARY ieee;\r
\r
USE ieee.std_logic_1164.ALL;\r
USE ieee.numeric_std.ALL;\r
\r
\r
entity USER_IO is\r
      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
             ADDR_REG : In    std_logic_vector (31 downto 0);\r
             CBE_REGn : In    std_logic_vector (3 downto 0);\r
                FLAG : In    std_logic_vector (7 downto 0);\r
             INT_REG : In    std_logic_vector (7 downto 0);\r
             IO_WR_COM : In    std_logic;\r
             IRDY_REGn : In    std_logic;\r
             PCI_CLK : In    std_logic;\r
             R_FIFO_Q : In    std_logic_vector (7 downto 0);\r
             READ_SEL : In    std_logic_vector (1 downto 0);\r
               TRDYn : In    std_logic;\r
             READ_XX1_0 : Out   std_logic;\r
             READ_XX3_2 : Out   std_logic;\r
             READ_XX5_4 : Out   std_logic;\r
             READ_XX7_6 : Out   std_logic;\r
             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);\r
             USER_DATA_OUT : Out   std_logic_vector (31 downto 0);\r
             WRITE_XX1_0 : Out   std_logic;\r
             WRITE_XX3_2 : Out   std_logic;\r
             WRITE_XX5_4 : Out   std_logic;\r
             WRITE_XX7_6 : Out   std_logic );\r
end USER_IO;\r
\r
architecture SCHEMATIC of USER_IO is\r
\r
   SIGNAL gnd : std_logic := '0';\r
   SIGNAL vcc : std_logic := '1';\r
\r
   signal WRITE_XX1_0_DUMMY : std_logic;\r
   signal WRITE_XX7_6_DUMMY : std_logic;\r
   signal REG_OUT_XX7_DUMMY : std_logic_vector (7 downto 0);\r
   signal REG_OUT_XX6_DUMMY : std_logic_vector (7 downto 0);\r
   signal REG_OUT_XX0_DUMMY : std_logic_vector (7 downto 0);\r
\r
   component IO_WR_SEL\r
      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);\r
             CBE_REGn : In    std_logic_vector (3 downto 0);\r
             IO_WR_COM : In    std_logic;\r
             IRDY_REGn : In    std_logic;\r
               TRDYn : In    std_logic;\r
             WRITE_XX1_0 : Out   std_logic;\r
             WRITE_XX3_2 : Out   std_logic;\r
             WRITE_XX5_4 : Out   std_logic;\r
             WRITE_XX7_6 : Out   std_logic );\r
   end component;\r
\r
   component DATA_MUX\r
      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);\r
             CBE_REGn : In    std_logic_vector (3 downto 0);\r
             MUX_IN_XX0 : In    std_logic_vector (7 downto 0);\r
             MUX_IN_XX1 : In    std_logic_vector (7 downto 0);\r
             MUX_IN_XX2 : In    std_logic_vector (7 downto 0);\r
             MUX_IN_XX3 : In    std_logic_vector (7 downto 0);\r
             MUX_IN_XX4 : In    std_logic_vector (7 downto 0);\r
             MUX_IN_XX5 : In    std_logic_vector (7 downto 0);\r
             MUX_IN_XX6 : In    std_logic_vector (7 downto 0);\r
             MUX_IN_XX7 : In    std_logic_vector (7 downto 0);\r
             READ_SEL : In    std_logic_vector (1 downto 0);\r
             MUX_OUT : Out   std_logic_vector (31 downto 0);\r
             READ_XX1_0 : Out   std_logic;\r
             READ_XX3_2 : Out   std_logic;\r
             READ_XX5_4 : Out   std_logic;\r
             READ_XX7_6 : Out   std_logic );\r
   end component;\r
\r
   component REG_IO\r
      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
               RESET : In    std_logic;\r
             WRITE_XX1_0 : In    std_logic;\r
             WRITE_XX7_6 : In    std_logic;\r
             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0) );\r
   end component;\r
\r
begin\r
\r
   REG_OUT_XX0 <= REG_OUT_XX0_DUMMY;\r
   REG_OUT_XX6 <= REG_OUT_XX6_DUMMY;\r
   REG_OUT_XX7 <= REG_OUT_XX7_DUMMY;\r
   WRITE_XX7_6 <= WRITE_XX7_6_DUMMY;\r
   WRITE_XX1_0 <= WRITE_XX1_0_DUMMY;\r
\r
   I4 : IO_WR_SEL\r
      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
                 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,\r
                 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0_DUMMY,\r
                 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
                 WRITE_XX7_6=>WRITE_XX7_6_DUMMY );\r
   I2 : DATA_MUX\r
      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
                 MUX_IN_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),\r
                 MUX_IN_XX1(7 downto 0)=>FLAG(7 downto 0),\r
                 MUX_IN_XX2(7 downto 0)=>R_FIFO_Q(7 downto 0),\r
                 MUX_IN_XX3(7 downto 0)=>FLAG(7 downto 0),\r
                 MUX_IN_XX4(7 downto 0)=>INT_REG(7 downto 0),\r
                 MUX_IN_XX5(7 downto 0)=>FLAG(7 downto 0),\r
                 MUX_IN_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),\r
                 MUX_IN_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0),\r
                 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
                 MUX_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
                 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
                 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6 );\r
   I1 : REG_IO\r
      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
                 PCI_CLOCK=>PCI_CLK, RESET=>REG_OUT_XX7_DUMMY(0),\r
                 WRITE_XX1_0=>WRITE_XX1_0_DUMMY,\r
                 WRITE_XX7_6=>WRITE_XX7_6_DUMMY,\r
                 REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),\r
                 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),\r
                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0) );\r
\r
end SCHEMATIC;\r
Commit	Line	Data
377c0242	1	-- VHDL model created from schematic user_io.sch -- Jan 09 09:34:12 2007\r
	2	\r
	3	\r
	4	\r
	5	LIBRARY ieee;\r
	6	\r
	7	USE ieee.std_logic_1164.ALL;\r
	8	USE ieee.numeric_std.ALL;\r
	9	\r
	10	\r
	11	entity USER_IO is\r
	12	Port ( AD_REG : In std_logic_vector (31 downto 0);\r
	13	ADDR_REG : In std_logic_vector (31 downto 0);\r
	14	CBE_REGn : In std_logic_vector (3 downto 0);\r
	15	FLAG : In std_logic_vector (7 downto 0);\r
	16	INT_REG : In std_logic_vector (7 downto 0);\r
	17	IO_WR_COM : In std_logic;\r
	18	IRDY_REGn : In std_logic;\r
	19	PCI_CLK : In std_logic;\r
	20	R_FIFO_Q : In std_logic_vector (7 downto 0);\r
	21	READ_SEL : In std_logic_vector (1 downto 0);\r
	22	TRDYn : In std_logic;\r
	23	READ_XX1_0 : Out std_logic;\r
	24	READ_XX3_2 : Out std_logic;\r
	25	READ_XX5_4 : Out std_logic;\r
	26	READ_XX7_6 : Out std_logic;\r
	27	REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
	28	REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
	29	REG_OUT_XX7 : Out std_logic_vector (7 downto 0);\r
	30	USER_DATA_OUT : Out std_logic_vector (31 downto 0);\r
	31	WRITE_XX1_0 : Out std_logic;\r
	32	WRITE_XX3_2 : Out std_logic;\r
	33	WRITE_XX5_4 : Out std_logic;\r
	34	WRITE_XX7_6 : Out std_logic );\r
	35	end USER_IO;\r
	36	\r
	37	architecture SCHEMATIC of USER_IO is\r
	38	\r
	39	SIGNAL gnd : std_logic := '0';\r
	40	SIGNAL vcc : std_logic := '1';\r
	41	\r
	42	signal WRITE_XX1_0_DUMMY : std_logic;\r
	43	signal WRITE_XX7_6_DUMMY : std_logic;\r
	44	signal REG_OUT_XX7_DUMMY : std_logic_vector (7 downto 0);\r
	45	signal REG_OUT_XX6_DUMMY : std_logic_vector (7 downto 0);\r
	46	signal REG_OUT_XX0_DUMMY : std_logic_vector (7 downto 0);\r
	47	\r
	48	component IO_WR_SEL\r
	49	Port ( ADDR_REG : In std_logic_vector (31 downto 0);\r
	50	CBE_REGn : In std_logic_vector (3 downto 0);\r
	51	IO_WR_COM : In std_logic;\r
	52	IRDY_REGn : In std_logic;\r
	53	TRDYn : In std_logic;\r
	54	WRITE_XX1_0 : Out std_logic;\r
	55	WRITE_XX3_2 : Out std_logic;\r
	56	WRITE_XX5_4 : Out std_logic;\r
	57	WRITE_XX7_6 : Out std_logic );\r
	58	end component;\r
	59	\r
	60	component DATA_MUX\r
	61	Port ( ADDR_REG : In std_logic_vector (31 downto 0);\r
	62	CBE_REGn : In std_logic_vector (3 downto 0);\r
	63	MUX_IN_XX0 : In std_logic_vector (7 downto 0);\r
	64	MUX_IN_XX1 : In std_logic_vector (7 downto 0);\r
65	MUX_IN_XX2 : In std_logic_vector (7 downto 0);\r
66	MUX_IN_XX3 : In std_logic_vector (7 downto 0);\r
67	MUX_IN_XX4 : In std_logic_vector (7 downto 0);\r
68	MUX_IN_XX5 : In std_logic_vector (7 downto 0);\r
69	MUX_IN_XX6 : In std_logic_vector (7 downto 0);\r
70	MUX_IN_XX7 : In std_logic_vector (7 downto 0);\r
71	READ_SEL : In std_logic_vector (1 downto 0);\r
72	MUX_OUT : Out std_logic_vector (31 downto 0);\r
73	READ_XX1_0 : Out std_logic;\r
74	READ_XX3_2 : Out std_logic;\r
75	READ_XX5_4 : Out std_logic;\r
76	READ_XX7_6 : Out std_logic );\r
77	end component;\r
78	\r
79	component REG_IO\r
80	Port ( AD_REG : In std_logic_vector (31 downto 0);\r
81	PCI_CLOCK : In std_logic;\r
82	RESET : In std_logic;\r
83	WRITE_XX1_0 : In std_logic;\r
84	WRITE_XX7_6 : In std_logic;\r
85	REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
86	REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
87	REG_OUT_XX7 : Out std_logic_vector (7 downto 0) );\r
88	end component;\r
89	\r
90	begin\r
91	\r
92	REG_OUT_XX0 <= REG_OUT_XX0_DUMMY;\r
93	REG_OUT_XX6 <= REG_OUT_XX6_DUMMY;\r
94	REG_OUT_XX7 <= REG_OUT_XX7_DUMMY;\r
95	WRITE_XX7_6 <= WRITE_XX7_6_DUMMY;\r
96	WRITE_XX1_0 <= WRITE_XX1_0_DUMMY;\r
97	\r
98	I4 : IO_WR_SEL\r
99	Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
100	CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
101	IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,\r
102	TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0_DUMMY,\r
103	WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
104	WRITE_XX7_6=>WRITE_XX7_6_DUMMY );\r
105	I2 : DATA_MUX\r
106	Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
107	CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
108	MUX_IN_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),\r
109	MUX_IN_XX1(7 downto 0)=>FLAG(7 downto 0),\r
110	MUX_IN_XX2(7 downto 0)=>R_FIFO_Q(7 downto 0),\r
111	MUX_IN_XX3(7 downto 0)=>FLAG(7 downto 0),\r
112	MUX_IN_XX4(7 downto 0)=>INT_REG(7 downto 0),\r
113	MUX_IN_XX5(7 downto 0)=>FLAG(7 downto 0),\r
114	MUX_IN_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),\r
115	MUX_IN_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0),\r
116	READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
117	MUX_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
118	READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
119	READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6 );\r
120	I1 : REG_IO\r
121	Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
122	PCI_CLOCK=>PCI_CLK, RESET=>REG_OUT_XX7_DUMMY(0),\r
123	WRITE_XX1_0=>WRITE_XX1_0_DUMMY,\r
124	WRITE_XX7_6=>WRITE_XX7_6_DUMMY,\r
125	REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),\r
126	REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),\r
127	REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0) );\r
128	\r
129	end SCHEMATIC;\r