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[raggedstone] / dhwk / source / Addr_regi.vhd

-- J.STELZNER\r
-- INFORMATIK-3 LABOR\r
-- 23.08.2006\r
-- File: ADDR_REG.VHD\r
\r
library IEEE;\r
use IEEE.std_logic_1164.all;\r
\r
entity ADDR_REGI is\r
	port\r
	(\r
	PCI_CLOCK			:in		std_logic;\r
	PCI_RSTn			:in		std_logic;\r
	LOAD_ADDR_REG	:in		std_logic;\r
	AD_REG				:in		std_logic_vector (31 downto 0);\r
	ADDR_REG			:out	std_logic_vector (31 downto 0)\r
  );\r
end entity ADDR_REGI;\r
\r
architecture ADDR_REGI_DESIGN of ADDR_REGI is\r
\r
	signal	REG_ADDR	:std_logic_vector (31 downto 0); \r
\r
begin \r
\r
	process (PCI_CLOCK, PCI_RSTn) \r
	begin\r
		if	PCI_RSTn = '0'	then	REG_ADDR	<= X"00000000";\r
\r
		elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
\r
			if LOAD_ADDR_REG = '1' then\r
						REG_ADDR	<=	AD_REG;\r
\r
			else	REG_ADDR	<=	REG_ADDR;\r
			end if;\r
\r
		end if;\r
	end process;\r
\r
	ADDR_REG	<=	REG_ADDR;\r
\r
end architecture ADDR_REGI_DESIGN;\r