[raggedstone] / dhwk / source / SER_PAR_CON.vhd

-- $Id: SER_PAR_CON.vhd,v 1.1 2007-03-10 11:24:03 sithglan Exp $\r
\r
library ieee;\r
use ieee.std_logic_1164.all;\r
use ieee.std_logic_unsigned.all;\r
\r
entity SER_PAR_CON is\r
	port\r
	(\r
	PCI_CLOCK			:in	std_logic; \r
	RESET				:in	std_logic; \r
	SPC_ENABLE			:in	std_logic; -- Driver Enable Sender/Receiver\r
	SYNC_R_FIFO_FFn                	:in	std_logic; -- FIFO Full Flag (low active)\r
 	SERIAL_IN			:in	std_logic; -- Serial Input\r
	R_FIFO_WRITEn		        :out	std_logic; -- FIFO Write (low active)\r
	SPC_RDY_OUT			:out	std_logic; -- Ready to Receive Data\r
	PAR_OUT				:out	std_logic_vector(7 downto 0)\r
	);\r
end entity SER_PAR_CON ;\r
\r
\r
architecture SER_PAR_CON_DESIGN of SER_PAR_CON is\r
\r
-- constant STATE_RECV            :std_logic_vector(3 downto 0) := "0001";\r
constant STATE_RECV_START_BIT  :std_logic_vector(3 downto 0) := "0010";\r
constant STATE_RECV_BIT_0      :std_logic_vector(3 downto 0) := "0011";\r
constant STATE_RECV_BIT_1      :std_logic_vector(3 downto 0) := "0100";\r
constant STATE_RECV_BIT_2      :std_logic_vector(3 downto 0) := "0101";\r
constant STATE_RECV_BIT_3      :std_logic_vector(3 downto 0) := "0110";\r
constant STATE_RECV_BIT_4      :std_logic_vector(3 downto 0) := "0111";\r
constant STATE_RECV_BIT_5      :std_logic_vector(3 downto 0) := "1000";\r
constant STATE_RECV_BIT_6      :std_logic_vector(3 downto 0) := "1001";\r
constant STATE_RECV_BIT_7      :std_logic_vector(3 downto 0) := "1010";\r
constant STATE_RECV_FIFOFULL   :std_logic_vector(3 downto 0) := "1011";\r
\r
signal COUNT     :std_logic_vector (3 downto 0);\r
signal STATE     :std_logic_vector (3 downto 0);\r
signal STARTBIT  :std_logic_vector (3 downto 0);\r
\r
\r
attribute syn_state_machine:boolean;\r
attribute syn_state_machine of STATE: signal is false;\r
attribute syn_state_machine of COUNT: signal is false;\r
\r
begin\r
\r
process(PCI_CLOCK)\r
begin\r
        if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
				    		if ("0000" < COUNT) then\r
                				COUNT <= COUNT - 1;\r
        				end if;\r
\r
-- war nicht das Problem des Datenverlusts\r
--        if (R_FIFO_WRITEn = '0' and COUNT = "0000") then\r
--            R_FIFO_WRITEn <= '1';\r
---      end if;\r
\r
                if (RESET = '1') then\r
                        STATE <= STATE_RECV_START_BIT;\r
                        COUNT <= "0000";\r
                        R_FIFO_WRITEn <= '1';\r
\r
                elsif (SPC_ENABLE = '1') then\r
                       \r
											 if (STATE = STATE_RECV_START_BIT) then\r
                              R_FIFO_WRITEn <= '1';\r
											        if (STARTBIT = "0011") then\r
																COUNT <= "0011";\r
                          	    STATE <= STATE_RECV_BIT_0;\r
                              end if;\r
\r
                       elsif (STATE = STATE_RECV_FIFOFULL) then\r
                              if (SYNC_R_FIFO_FFn = '1') then\r
                                      R_FIFO_WRITEn <= '0';\r
                                      STATE <= STATE_RECV_START_BIT;\r
                              end if;\r
\r
                       elsif (COUNT = "0000") then\r
                        COUNT <= "0011";\r
                        case STATE is\r
																\r
                                when STATE_RECV_BIT_0 =>\r
                                        PAR_OUT(0) <= STARTBIT(0);\r
                                        STATE <= STATE_RECV_BIT_1;\r
\r
                                when STATE_RECV_BIT_1 =>\r
                                        PAR_OUT(1) <= STARTBIT(0);\r
                                        STATE <= STATE_RECV_BIT_2;\r
                                        \r
                                when STATE_RECV_BIT_2 =>\r
                                        PAR_OUT(2) <= STARTBIT(0);\r
                                        STATE <= STATE_RECV_BIT_3;\r
                                        \r
                                when STATE_RECV_BIT_3 =>\r
                                        PAR_OUT(3) <= STARTBIT(0);\r
                                        STATE <= STATE_RECV_BIT_4;\r
                                        \r
                                when STATE_RECV_BIT_4 =>\r
                                        PAR_OUT(4) <= STARTBIT(0);\r
                                        STATE <= STATE_RECV_BIT_5;\r
                                        \r
                                when STATE_RECV_BIT_5 =>\r
                                        PAR_OUT(5) <= STARTBIT(0);\r
                                        STATE <= STATE_RECV_BIT_6;\r
                                        \r
                                when STATE_RECV_BIT_6 =>\r
                                        PAR_OUT(6) <= STARTBIT(0);\r
                                        STATE <= STATE_RECV_BIT_7;\r
                                        \r
                                when STATE_RECV_BIT_7 =>\r
                                        PAR_OUT(7) <= STARTBIT(0);\r
\r
                                        if (SYNC_R_FIFO_FFn = '1') then\r
                                             STATE <= STATE_RECV_START_BIT;\r
                                             R_FIFO_WRITEn <= '0';\r
                                        else \r
                                             STATE <= STATE_RECV_FIFOFULL;\r
                                        end if;\r
\r
																when others =>\r
																				STATE <= STATE_RECV_START_BIT;\r
\r
                        end case;\r
                     end if; -- COUNT\r
                end if; -- RESET ... / SPC_ENABLE ...\r
        end if; -- PCI_CLOCK ...\r
end process;\r
\r
process(PCI_CLOCK)\r
begin\r
		if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
      SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;\r
		end if;\r
end process;\r
\r
\r
process(PCI_CLOCK)\r
begin\r
        if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
					if (RESET = '1') then\r
 						STARTBIT <= "0000";\r
					else\r
					STARTBIT(0) <= SERIAL_IN;\r
					STARTBIT(1) <= STARTBIT(0);\r
					STARTBIT(2) <= STARTBIT(1);\r
					STARTBIT(3) <= STARTBIT(2);\r
					end if;				  \r
  			end if;\r
end process;\r
\r
\r
\r
end architecture SER_PAR_CON_DESIGN;\r
Commit	Line	Data
377c0242	1	-- $Id: SER_PAR_CON.vhd,v 1.1 2007-03-10 11:24:03 sithglan Exp $\r
	2	\r
	3	library ieee;\r
	4	use ieee.std_logic_1164.all;\r
	5	use ieee.std_logic_unsigned.all;\r
	6	\r
	7	entity SER_PAR_CON is\r
	8	port\r
	9	(\r
	10	PCI_CLOCK :in std_logic; \r
	11	RESET :in std_logic; \r
	12	SPC_ENABLE :in std_logic; -- Driver Enable Sender/Receiver\r
	13	SYNC_R_FIFO_FFn :in std_logic; -- FIFO Full Flag (low active)\r
	14	SERIAL_IN :in std_logic; -- Serial Input\r
	15	R_FIFO_WRITEn :out std_logic; -- FIFO Write (low active)\r
	16	SPC_RDY_OUT :out std_logic; -- Ready to Receive Data\r
	17	PAR_OUT :out std_logic_vector(7 downto 0)\r
	18	);\r
	19	end entity SER_PAR_CON ;\r
	20	\r
	21	\r
	22	architecture SER_PAR_CON_DESIGN of SER_PAR_CON is\r
	23	\r
	24	-- constant STATE_RECV :std_logic_vector(3 downto 0) := "0001";\r
	25	constant STATE_RECV_START_BIT :std_logic_vector(3 downto 0) := "0010";\r
	26	constant STATE_RECV_BIT_0 :std_logic_vector(3 downto 0) := "0011";\r
	27	constant STATE_RECV_BIT_1 :std_logic_vector(3 downto 0) := "0100";\r
	28	constant STATE_RECV_BIT_2 :std_logic_vector(3 downto 0) := "0101";\r
	29	constant STATE_RECV_BIT_3 :std_logic_vector(3 downto 0) := "0110";\r
	30	constant STATE_RECV_BIT_4 :std_logic_vector(3 downto 0) := "0111";\r
	31	constant STATE_RECV_BIT_5 :std_logic_vector(3 downto 0) := "1000";\r
	32	constant STATE_RECV_BIT_6 :std_logic_vector(3 downto 0) := "1001";\r
	33	constant STATE_RECV_BIT_7 :std_logic_vector(3 downto 0) := "1010";\r
	34	constant STATE_RECV_FIFOFULL :std_logic_vector(3 downto 0) := "1011";\r
	35	\r
	36	signal COUNT :std_logic_vector (3 downto 0);\r
	37	signal STATE :std_logic_vector (3 downto 0);\r
	38	signal STARTBIT :std_logic_vector (3 downto 0);\r
	39	\r
	40	\r
	41	attribute syn_state_machine:boolean;\r
	42	attribute syn_state_machine of STATE: signal is false;\r
	43	attribute syn_state_machine of COUNT: signal is false;\r
	44	\r
	45	begin\r
	46	\r
	47	process(PCI_CLOCK)\r
	48	begin\r
	49	if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
	50	if ("0000" < COUNT) then\r
	51	COUNT <= COUNT - 1;\r
	52	end if;\r
	53	\r
	54	-- war nicht das Problem des Datenverlusts\r
	55	-- if (R_FIFO_WRITEn = '0' and COUNT = "0000") then\r
	56	-- R_FIFO_WRITEn <= '1';\r
	57	--- end if;\r
	58	\r
	59	if (RESET = '1') then\r
	60	STATE <= STATE_RECV_START_BIT;\r
	61	COUNT <= "0000";\r
	62	R_FIFO_WRITEn <= '1';\r
	63	\r
	64	elsif (SPC_ENABLE = '1') then\r
65	\r
66	if (STATE = STATE_RECV_START_BIT) then\r
67	R_FIFO_WRITEn <= '1';\r
68	if (STARTBIT = "0011") then\r
69	COUNT <= "0011";\r
70	STATE <= STATE_RECV_BIT_0;\r
71	end if;\r
72	\r
73	elsif (STATE = STATE_RECV_FIFOFULL) then\r
74	if (SYNC_R_FIFO_FFn = '1') then\r
75	R_FIFO_WRITEn <= '0';\r
76	STATE <= STATE_RECV_START_BIT;\r
77	end if;\r
78	\r
79	elsif (COUNT = "0000") then\r
80	COUNT <= "0011";\r
81	case STATE is\r
82	\r
83	when STATE_RECV_BIT_0 =>\r
84	PAR_OUT(0) <= STARTBIT(0);\r
85	STATE <= STATE_RECV_BIT_1;\r
86	\r
87	when STATE_RECV_BIT_1 =>\r
88	PAR_OUT(1) <= STARTBIT(0);\r
89	STATE <= STATE_RECV_BIT_2;\r
90	\r
91	when STATE_RECV_BIT_2 =>\r
92	PAR_OUT(2) <= STARTBIT(0);\r
93	STATE <= STATE_RECV_BIT_3;\r
94	\r
95	when STATE_RECV_BIT_3 =>\r
96	PAR_OUT(3) <= STARTBIT(0);\r
97	STATE <= STATE_RECV_BIT_4;\r
98	\r
99	when STATE_RECV_BIT_4 =>\r
100	PAR_OUT(4) <= STARTBIT(0);\r
101	STATE <= STATE_RECV_BIT_5;\r
102	\r
103	when STATE_RECV_BIT_5 =>\r
104	PAR_OUT(5) <= STARTBIT(0);\r
105	STATE <= STATE_RECV_BIT_6;\r
106	\r
107	when STATE_RECV_BIT_6 =>\r
108	PAR_OUT(6) <= STARTBIT(0);\r
109	STATE <= STATE_RECV_BIT_7;\r
110	\r
111	when STATE_RECV_BIT_7 =>\r
112	PAR_OUT(7) <= STARTBIT(0);\r
113	\r
114	if (SYNC_R_FIFO_FFn = '1') then\r
115	STATE <= STATE_RECV_START_BIT;\r
116	R_FIFO_WRITEn <= '0';\r
117	else \r
118	STATE <= STATE_RECV_FIFOFULL;\r
119	end if;\r
120	\r
121	when others =>\r
122	STATE <= STATE_RECV_START_BIT;\r
123	\r
124	end case;\r
125	end if; -- COUNT\r
126	end if; -- RESET ... / SPC_ENABLE ...\r
127	end if; -- PCI_CLOCK ...\r
128	end process;\r
129	\r
130	process(PCI_CLOCK)\r
131	begin\r
132	if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
133	SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;\r
134	end if;\r
135	end process;\r
136	\r
137	\r
138	process(PCI_CLOCK)\r
139	begin\r
140	if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
141	if (RESET = '1') then\r
142	STARTBIT <= "0000";\r
143	else\r
144	STARTBIT(0) <= SERIAL_IN;\r
145	STARTBIT(1) <= STARTBIT(0);\r
146	STARTBIT(2) <= STARTBIT(1);\r
147	STARTBIT(3) <= STARTBIT(2);\r
148	end if; \r
149	end if;\r
150	end process;\r
151	\r
152	\r
153	\r
154	end architecture SER_PAR_CON_DESIGN;\r