level

[raggedstone] / dhwk / source / Verg_2.vhd

-- J.STELZNER\r
-- INFORMATIK-3 LABOR\r
-- 23.08.2006\r
-- File: VERG_2.VHD\r
\r
library ieee ;\r
use ieee.std_logic_1164.all ;\r
\r
entity	VERG_2	is\r
	port\r
	(\r
 	IN_A		:in		std_logic_vector(1 downto 0);\r
 	IN_B		:in		std_logic_vector(1 downto 0);\r
	GLEICH	:out	std_logic\r
	);\r
end entity VERG_2 ;\r
\r
architecture VERG_2_DESIGN of VERG_2 is\r
\r
begin\r
\r
	process (IN_A,IN_B) \r
	begin \r
\r
		if			IN_A	=	IN_B	then	GLEICH	<=	'1';\r
			else											GLEICH	<=	'0';   \r
		end if;\r
\r
	end process;\r
\r
end architecture VERG_2_DESIGN ;\r