[raggedstone] / dhwk / source / pci_interface.vhd

-- VHDL model created from schematic pci_interface.sch -- Jan 09 09:34:13 2007\r
\r
\r
\r
LIBRARY ieee;\r
\r
USE ieee.std_logic_1164.ALL;\r
USE ieee.numeric_std.ALL;\r
\r
\r
entity PCI_INTERFACE is\r
      Port ( PCI_CBEn : In    std_logic_vector (3 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
             PCI_FRAMEn : In    std_logic;\r
             PCI_IDSEL : In    std_logic;\r
             PCI_IRDYn : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
             READ_FIFO : In    std_logic;\r
             REVISON_ID : In    std_logic_vector (7 downto 0);\r
             USER_DATA_OUT : In    std_logic_vector (31 downto 0);\r
             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
              PCI_AD : InOut std_logic_vector (31 downto 0);\r
             PCI_PAR : InOut std_logic;\r
              AD_REG : Out   std_logic_vector (31 downto 0);\r
             ADDR_REG : Out   std_logic_vector (31 downto 0);\r
             CBE_REGn : Out   std_logic_vector (3 downto 0);\r
             DEVSELn : Out   std_logic;\r
             FIFO_RDn : Out   std_logic;\r
             IO_WR_COM : Out   std_logic;\r
             IRDY_REGn : Out   std_logic;\r
             PCI_DEVSELn : Out   std_logic;\r
             PCI_PERRn : Out   std_logic;\r
             PCI_SERRn : Out   std_logic;\r
             PCI_STOPn : Out   std_logic;\r
             PCI_TRDYn : Out   std_logic;\r
             READ_SEL : Out   std_logic_vector (1 downto 0);\r
               TRDYn : Out   std_logic );\r
end PCI_INTERFACE;\r
\r
architecture SCHEMATIC of PCI_INTERFACE is\r
\r
   SIGNAL gnd : std_logic := '0';\r
   SIGNAL vcc : std_logic := '1';\r
\r
   signal IRDY_REGn_DUMMY : std_logic;\r
   signal  PAR_REG : std_logic;\r
   signal     PERR : std_logic;\r
   signal     SERR : std_logic;\r
   signal CF_RD_COM : std_logic;\r
   signal CF_WR_COM : std_logic;\r
   signal      LAR : std_logic;\r
   signal  MY_ADDR : std_logic;\r
   signal SERR_CHECK : std_logic;\r
   signal IDSEL_REG : std_logic;\r
   signal FRAME_REGn : std_logic;\r
   signal PERR_CHECK : std_logic;\r
   signal OE_PCI_PAR : std_logic;\r
   signal OE_PCI_PERR : std_logic;\r
   signal TRDYn_DUMMY : std_logic;\r
   signal CONF_DATA_10H : std_logic_vector (31 downto 0);\r
   signal CONF_DATA_04H : std_logic_vector (31 downto 0);\r
   signal CONF_DATA : std_logic_vector (31 downto 0);\r
   signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);\r
   signal CBE_REGn_DUMMY : std_logic_vector (3 downto 0);\r
   signal AD_REG_DUMMY : std_logic_vector (31 downto 0);\r
   signal ADDR_REG_DUMMY : std_logic_vector (31 downto 0);\r
\r
   component STEUERUNG\r
      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
             CBE_REGn : In    std_logic_vector (3 downto 0);\r
             FRAME_REGn : In    std_logic;\r
             IDSEL_REG : In    std_logic;\r
             IO_SPACE : In    std_logic;\r
             MY_ADDR : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
             READ_FIFO : In    std_logic;\r
             CF_RD_COM : Out   std_logic;\r
             CF_WR_COM : Out   std_logic;\r
             DEVSELn : Out   std_logic;\r
             FIFO_RDn : Out   std_logic;\r
             IO_RD_COM : Out   std_logic;\r
             IO_WR_COM : Out   std_logic;\r
                 LAR : Out   std_logic;\r
             OE_PCI_PAR : Out   std_logic;\r
             OE_PCI_PERR : Out   std_logic;\r
             PCI_DEVSELn : Out   std_logic;\r
             PCI_STOPn : Out   std_logic;\r
             PCI_TRDYn : Out   std_logic;\r
             PERR_CHECK : Out   std_logic;\r
                READ : Out   std_logic;\r
             SERR_CHECK : Out   std_logic;\r
               TRDYn : Out   std_logic );\r
   end component;\r
\r
   component PARITY\r
      Port ( OE_PCI_PAR : In    std_logic;\r
             OE_PCI_PERR : In    std_logic;\r
             PA_ER_RE : In    std_logic;\r
              PAR_IN : In    std_logic_vector (35 downto 0);\r
             PAR_REG : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
             PERR_CHECK : In    std_logic;\r
             SERR_CHECK : In    std_logic;\r
             SERR_ENA : In    std_logic;\r
             PCI_PAR : InOut std_logic;\r
             PCI_PERRn : Out   std_logic;\r
             PCI_SERRn : Out   std_logic;\r
                PERR : Out   std_logic;\r
                SERR : Out   std_logic );\r
   end component;\r
\r
   component VERGLEICH\r
      Port (    IN_A : In    std_logic_vector (31 downto 0);\r
                IN_B : In    std_logic_vector (31 downto 0);\r
             GLEICH_OUT : Out   std_logic );\r
   end component;\r
\r
   component IO_MUX_REG\r
      Port ( CONFIG_DATA : In    std_logic_vector (31 downto 0);\r
             LOAD_ADDR_REG : In    std_logic;\r
             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
             PCI_FRAMEn : In    std_logic;\r
             PCI_IDSEL : In    std_logic;\r
             PCI_IRDYn : In    std_logic;\r
             PCI_PAR : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
             READ_SEL : In    std_logic_vector (1 downto 0);\r
             USER_DATA : In    std_logic_vector (31 downto 0);\r
              PCI_AD : InOut std_logic_vector (31 downto 0);\r
              AD_REG : Out   std_logic_vector (31 downto 0);\r
             ADDR_REG : Out   std_logic_vector (31 downto 0);\r
             CBE_REGn : Out   std_logic_vector (3 downto 0);\r
             FRAME_REGn : Out   std_logic;\r
             IDSEL_REG : Out   std_logic;\r
             IRDY_REGn : Out   std_logic;\r
             PAR_REG : Out   std_logic );\r
   end component;\r
\r
   component CONFIG_SPACE_HEADER\r
      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
             ADDR_REG : In    std_logic_vector (31 downto 0);\r
             CBE_REGn : In    std_logic_vector (3 downto 0);\r
             CF_RD_COM : In    std_logic;\r
             CF_WR_COM : In    std_logic;\r
             IRDY_REGn : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
                PERR : In    std_logic;\r
             REVISION_ID : In    std_logic_vector (7 downto 0);\r
                SERR : In    std_logic;\r
               TRDYn : In    std_logic;\r
             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
             CONF_DATA : Out   std_logic_vector (31 downto 0);\r
             CONF_DATA_04H : Out   std_logic_vector (31 downto 0);\r
             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );\r
   end component;\r
\r
begin\r
\r
   ADDR_REG <= ADDR_REG_DUMMY;\r
   AD_REG <= AD_REG_DUMMY;\r
   CBE_REGn <= CBE_REGn_DUMMY;\r
   READ_SEL <= READ_SEL_DUMMY;\r
   TRDYn <= TRDYn_DUMMY;\r
   IRDY_REGn <= IRDY_REGn_DUMMY;\r
\r
   I7 : STEUERUNG\r
      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
                 CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),\r
                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
                 IO_SPACE=>CONF_DATA_04H(0), MY_ADDR=>MY_ADDR,\r
                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
                 READ_FIFO=>READ_FIFO, CF_RD_COM=>CF_RD_COM,\r
                 CF_WR_COM=>CF_WR_COM, DEVSELn=>DEVSELn,\r
                 FIFO_RDn=>FIFO_RDn, IO_RD_COM=>READ_SEL_DUMMY(0),\r
                 IO_WR_COM=>IO_WR_COM, LAR=>LAR, OE_PCI_PAR=>OE_PCI_PAR,\r
                 OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,\r
                 PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,\r
                 PERR_CHECK=>PERR_CHECK, READ=>READ_SEL_DUMMY(1),\r
                 SERR_CHECK=>SERR_CHECK, TRDYn=>TRDYn_DUMMY );\r
   I5 : PARITY\r
      Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,\r
                 PA_ER_RE=>CONF_DATA_04H(6),\r
                 PAR_IN(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
                 PAR_IN(35 downto 32)=>CBE_REGn_DUMMY(3 downto 0),\r
                 PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,\r
                 PCI_RSTn=>PCI_RSTn, PERR_CHECK=>PERR_CHECK,\r
                 SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8),\r
                 PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn,\r
                 PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR );\r
   I4 : VERGLEICH\r
      Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0),\r
                 IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
                 GLEICH_OUT=>MY_ADDR );\r
   I2 : IO_MUX_REG\r
      Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0),\r
                 LOAD_ADDR_REG=>LAR,\r
                 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
                 PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,\r
                 READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),\r
                 USER_DATA(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
                 AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
                 ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),\r
                 CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),\r
                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
                 IRDY_REGn=>IRDY_REGn_DUMMY, PAR_REG=>PAR_REG );\r
   I1 : CONFIG_SPACE_HEADER\r
      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
                 ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),\r
                 CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),\r
                 CF_RD_COM=>CF_RD_COM, CF_WR_COM=>CF_WR_COM,\r
                 IRDY_REGn=>IRDY_REGn_DUMMY, PCI_CLOCK=>PCI_CLOCK,\r
                 PCI_RSTn=>PCI_RSTn, PERR=>PERR,\r
                 REVISION_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
                 SERR=>SERR, TRDYn=>TRDYn_DUMMY,\r
                 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
                 CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0),\r
                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0),\r
                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) );\r
\r
end SCHEMATIC;\r
Commit	Line	Data
377c0242	1	-- VHDL model created from schematic pci_interface.sch -- Jan 09 09:34:13 2007\r
	2	\r
	3	\r
	4	\r
	5	LIBRARY ieee;\r
	6	\r
	7	USE ieee.std_logic_1164.ALL;\r
	8	USE ieee.numeric_std.ALL;\r
	9	\r
	10	\r
	11	entity PCI_INTERFACE is\r
	12	Port ( PCI_CBEn : In std_logic_vector (3 downto 0);\r
	13	PCI_CLOCK : In std_logic;\r
	14	PCI_FRAMEn : In std_logic;\r
	15	PCI_IDSEL : In std_logic;\r
	16	PCI_IRDYn : In std_logic;\r
	17	PCI_RSTn : In std_logic;\r
	18	READ_FIFO : In std_logic;\r
	19	REVISON_ID : In std_logic_vector (7 downto 0);\r
	20	USER_DATA_OUT : In std_logic_vector (31 downto 0);\r
	21	VENDOR_ID : In std_logic_vector (15 downto 0);\r
	22	PCI_AD : InOut std_logic_vector (31 downto 0);\r
	23	PCI_PAR : InOut std_logic;\r
	24	AD_REG : Out std_logic_vector (31 downto 0);\r
	25	ADDR_REG : Out std_logic_vector (31 downto 0);\r
	26	CBE_REGn : Out std_logic_vector (3 downto 0);\r
	27	DEVSELn : Out std_logic;\r
	28	FIFO_RDn : Out std_logic;\r
	29	IO_WR_COM : Out std_logic;\r
	30	IRDY_REGn : Out std_logic;\r
	31	PCI_DEVSELn : Out std_logic;\r
	32	PCI_PERRn : Out std_logic;\r
	33	PCI_SERRn : Out std_logic;\r
	34	PCI_STOPn : Out std_logic;\r
	35	PCI_TRDYn : Out std_logic;\r
	36	READ_SEL : Out std_logic_vector (1 downto 0);\r
	37	TRDYn : Out std_logic );\r
	38	end PCI_INTERFACE;\r
	39	\r
	40	architecture SCHEMATIC of PCI_INTERFACE is\r
	41	\r
	42	SIGNAL gnd : std_logic := '0';\r
	43	SIGNAL vcc : std_logic := '1';\r
	44	\r
	45	signal IRDY_REGn_DUMMY : std_logic;\r
	46	signal PAR_REG : std_logic;\r
	47	signal PERR : std_logic;\r
	48	signal SERR : std_logic;\r
	49	signal CF_RD_COM : std_logic;\r
	50	signal CF_WR_COM : std_logic;\r
	51	signal LAR : std_logic;\r
	52	signal MY_ADDR : std_logic;\r
	53	signal SERR_CHECK : std_logic;\r
	54	signal IDSEL_REG : std_logic;\r
	55	signal FRAME_REGn : std_logic;\r
	56	signal PERR_CHECK : std_logic;\r
	57	signal OE_PCI_PAR : std_logic;\r
	58	signal OE_PCI_PERR : std_logic;\r
	59	signal TRDYn_DUMMY : std_logic;\r
	60	signal CONF_DATA_10H : std_logic_vector (31 downto 0);\r
	61	signal CONF_DATA_04H : std_logic_vector (31 downto 0);\r
	62	signal CONF_DATA : std_logic_vector (31 downto 0);\r
	63	signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);\r
	64	signal CBE_REGn_DUMMY : std_logic_vector (3 downto 0);\r
65	signal AD_REG_DUMMY : std_logic_vector (31 downto 0);\r
66	signal ADDR_REG_DUMMY : std_logic_vector (31 downto 0);\r
67	\r
68	component STEUERUNG\r
69	Port ( AD_REG : In std_logic_vector (31 downto 0);\r
70	CBE_REGn : In std_logic_vector (3 downto 0);\r
71	FRAME_REGn : In std_logic;\r
72	IDSEL_REG : In std_logic;\r
73	IO_SPACE : In std_logic;\r
74	MY_ADDR : In std_logic;\r
75	PCI_CLOCK : In std_logic;\r
76	PCI_RSTn : In std_logic;\r
77	READ_FIFO : In std_logic;\r
78	CF_RD_COM : Out std_logic;\r
79	CF_WR_COM : Out std_logic;\r
80	DEVSELn : Out std_logic;\r
81	FIFO_RDn : Out std_logic;\r
82	IO_RD_COM : Out std_logic;\r
83	IO_WR_COM : Out std_logic;\r
84	LAR : Out std_logic;\r
85	OE_PCI_PAR : Out std_logic;\r
86	OE_PCI_PERR : Out std_logic;\r
87	PCI_DEVSELn : Out std_logic;\r
88	PCI_STOPn : Out std_logic;\r
89	PCI_TRDYn : Out std_logic;\r
90	PERR_CHECK : Out std_logic;\r
91	READ : Out std_logic;\r
92	SERR_CHECK : Out std_logic;\r
93	TRDYn : Out std_logic );\r
94	end component;\r
95	\r
96	component PARITY\r
97	Port ( OE_PCI_PAR : In std_logic;\r
98	OE_PCI_PERR : In std_logic;\r
99	PA_ER_RE : In std_logic;\r
100	PAR_IN : In std_logic_vector (35 downto 0);\r
101	PAR_REG : In std_logic;\r
102	PCI_CLOCK : In std_logic;\r
103	PCI_RSTn : In std_logic;\r
104	PERR_CHECK : In std_logic;\r
105	SERR_CHECK : In std_logic;\r
106	SERR_ENA : In std_logic;\r
107	PCI_PAR : InOut std_logic;\r
108	PCI_PERRn : Out std_logic;\r
109	PCI_SERRn : Out std_logic;\r
110	PERR : Out std_logic;\r
111	SERR : Out std_logic );\r
112	end component;\r
113	\r
114	component VERGLEICH\r
115	Port ( IN_A : In std_logic_vector (31 downto 0);\r
116	IN_B : In std_logic_vector (31 downto 0);\r
117	GLEICH_OUT : Out std_logic );\r
118	end component;\r
119	\r
120	component IO_MUX_REG\r
121	Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);\r
122	LOAD_ADDR_REG : In std_logic;\r
123	PCI_CBEn : In std_logic_vector (3 downto 0);\r
124	PCI_CLOCK : In std_logic;\r
125	PCI_FRAMEn : In std_logic;\r
126	PCI_IDSEL : In std_logic;\r
127	PCI_IRDYn : In std_logic;\r
128	PCI_PAR : In std_logic;\r
129	PCI_RSTn : In std_logic;\r
130	READ_SEL : In std_logic_vector (1 downto 0);\r
131	USER_DATA : In std_logic_vector (31 downto 0);\r
132	PCI_AD : InOut std_logic_vector (31 downto 0);\r
133	AD_REG : Out std_logic_vector (31 downto 0);\r
134	ADDR_REG : Out std_logic_vector (31 downto 0);\r
135	CBE_REGn : Out std_logic_vector (3 downto 0);\r
136	FRAME_REGn : Out std_logic;\r
137	IDSEL_REG : Out std_logic;\r
138	IRDY_REGn : Out std_logic;\r
139	PAR_REG : Out std_logic );\r
140	end component;\r
141	\r
142	component CONFIG_SPACE_HEADER\r
143	Port ( AD_REG : In std_logic_vector (31 downto 0);\r
144	ADDR_REG : In std_logic_vector (31 downto 0);\r
145	CBE_REGn : In std_logic_vector (3 downto 0);\r
146	CF_RD_COM : In std_logic;\r
147	CF_WR_COM : In std_logic;\r
148	IRDY_REGn : In std_logic;\r
149	PCI_CLOCK : In std_logic;\r
150	PCI_RSTn : In std_logic;\r
151	PERR : In std_logic;\r
152	REVISION_ID : In std_logic_vector (7 downto 0);\r
153	SERR : In std_logic;\r
154	TRDYn : In std_logic;\r
155	VENDOR_ID : In std_logic_vector (15 downto 0);\r
156	CONF_DATA : Out std_logic_vector (31 downto 0);\r
157	CONF_DATA_04H : Out std_logic_vector (31 downto 0);\r
158	CONF_DATA_10H : Out std_logic_vector (31 downto 0) );\r
159	end component;\r
160	\r
161	begin\r
162	\r
163	ADDR_REG <= ADDR_REG_DUMMY;\r
164	AD_REG <= AD_REG_DUMMY;\r
165	CBE_REGn <= CBE_REGn_DUMMY;\r
166	READ_SEL <= READ_SEL_DUMMY;\r
167	TRDYn <= TRDYn_DUMMY;\r
168	IRDY_REGn <= IRDY_REGn_DUMMY;\r
169	\r
170	I7 : STEUERUNG\r
171	Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
172	CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),\r
173	FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
174	IO_SPACE=>CONF_DATA_04H(0), MY_ADDR=>MY_ADDR,\r
175	PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
176	READ_FIFO=>READ_FIFO, CF_RD_COM=>CF_RD_COM,\r
177	CF_WR_COM=>CF_WR_COM, DEVSELn=>DEVSELn,\r
178	FIFO_RDn=>FIFO_RDn, IO_RD_COM=>READ_SEL_DUMMY(0),\r
179	IO_WR_COM=>IO_WR_COM, LAR=>LAR, OE_PCI_PAR=>OE_PCI_PAR,\r
180	OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,\r
181	PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,\r
182	PERR_CHECK=>PERR_CHECK, READ=>READ_SEL_DUMMY(1),\r
183	SERR_CHECK=>SERR_CHECK, TRDYn=>TRDYn_DUMMY );\r
184	I5 : PARITY\r
185	Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,\r
186	PA_ER_RE=>CONF_DATA_04H(6),\r
187	PAR_IN(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
188	PAR_IN(35 downto 32)=>CBE_REGn_DUMMY(3 downto 0),\r
189	PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,\r
190	PCI_RSTn=>PCI_RSTn, PERR_CHECK=>PERR_CHECK,\r
191	SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8),\r
192	PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn,\r
193	PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR );\r
194	I4 : VERGLEICH\r
195	Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0),\r
196	IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
197	GLEICH_OUT=>MY_ADDR );\r
198	I2 : IO_MUX_REG\r
199	Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0),\r
200	LOAD_ADDR_REG=>LAR,\r
201	PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
202	PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
203	PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
204	PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,\r
205	READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),\r
206	USER_DATA(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
207	PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
208	AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
209	ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),\r
210	CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),\r
211	FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
212	IRDY_REGn=>IRDY_REGn_DUMMY, PAR_REG=>PAR_REG );\r
213	I1 : CONFIG_SPACE_HEADER\r
214	Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
215	ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),\r
216	CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),\r
217	CF_RD_COM=>CF_RD_COM, CF_WR_COM=>CF_WR_COM,\r
218	IRDY_REGn=>IRDY_REGn_DUMMY, PCI_CLOCK=>PCI_CLOCK,\r
219	PCI_RSTn=>PCI_RSTn, PERR=>PERR,\r
220	REVISION_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
221	SERR=>SERR, TRDYn=>TRDYn_DUMMY,\r
222	VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
223	CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0),\r
224	CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0),\r
225	CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) );\r
226	\r
227	end SCHEMATIC;\r