[raggedstone] / dhwk / source / steuerung.vhd

-- VHDL model created from schematic steuerung.sch -- Jan 09 09:34:14 2007\r
\r
-- LIBRARY vanmacro;\r
-- USE vanmacro.components.ALL;\r
LIBRARY ieee;\r
--LIBRARY generics;\r
USE ieee.std_logic_1164.ALL;\r
USE ieee.numeric_std.ALL;\r
--USE generics.components.ALL;\r
\r
entity STEUERUNG is\r
      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
             CBE_REGn : In    std_logic_vector (3 downto 0);\r
             FRAME_REGn : In    std_logic;\r
             IDSEL_REG : In    std_logic;\r
             IO_SPACE : In    std_logic;\r
             MY_ADDR : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
             READ_FIFO : In    std_logic;\r
             CF_RD_COM : Out   std_logic;\r
             CF_WR_COM : Out   std_logic;\r
             DEVSELn : Out   std_logic;\r
             FIFO_RDn : Out   std_logic;\r
             IO_RD_COM : Out   std_logic;\r
             IO_WR_COM : Out   std_logic;\r
                 LAR : Out   std_logic;\r
             OE_PCI_PAR : Out   std_logic;\r
             OE_PCI_PERR : Out   std_logic;\r
             PCI_DEVSELn : Out   std_logic;\r
             PCI_STOPn : Out   std_logic;\r
             PCI_TRDYn : Out   std_logic;\r
             PERR_CHECK : Out   std_logic;\r
                READ : Out   std_logic;\r
             SERR_CHECK : Out   std_logic;\r
               TRDYn : Out   std_logic );\r
end STEUERUNG;\r
\r
architecture SCHEMATIC of STEUERUNG is\r
\r
   SIGNAL gnd : std_logic := '0';\r
   SIGNAL vcc : std_logic := '1';\r
\r
   signal DEVSELn_DUMMY : std_logic;\r
   signal  IO_READ : std_logic;\r
   signal IO_WRITE : std_logic;\r
   signal CONF_READ : std_logic;\r
   signal CONF_WRITE : std_logic;\r
\r
   component CONT_FSM\r
      Port ( CONF_READ : In    std_logic;\r
             CONF_WRITE : In    std_logic;\r
             FIFO_READ : In    std_logic;\r
             IO_READ : In    std_logic;\r
             IO_WRITE : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
             DEVSELn : Out   std_logic;\r
             FIFO_RDn : Out   std_logic;\r
             OE_PCI_PAR : Out   std_logic;\r
             OE_PCI_PERR : Out   std_logic;\r
             PCI_DEVSELn : Out   std_logic;\r
             PCI_STOPn : Out   std_logic;\r
             PCI_TRDYn : Out   std_logic;\r
             PERR_CHECK : Out   std_logic;\r
                READ : Out   std_logic;\r
               TRDYn : Out   std_logic );\r
   end component;\r
\r
   component COMM_FSM\r
      Port ( CONF_READ : In    std_logic;\r
             CONF_WRITE : In    std_logic;\r
             DEVSELn : In    std_logic;\r
             IO_READ : In    std_logic;\r
             IO_WRITE : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
             CF_RD_COM : Out   std_logic;\r
             CF_WR_COM : Out   std_logic;\r
             IO_RD_COM : Out   std_logic;\r
             IO_WR_COM : Out   std_logic );\r
   end component;\r
\r
   component COMM_DEC\r
      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
             CBE_REGn : In    std_logic_vector (3 downto 0);\r
             FRAME_REGn : In    std_logic;\r
             IDSEL_REG : In    std_logic;\r
             IO_SPACE : In    std_logic;\r
             MY_ADDR : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
             CONF_READ : Out   std_logic;\r
             CONF_WRITE : Out   std_logic;\r
             IO_READ : Out   std_logic;\r
             IO_WRITE : Out   std_logic;\r
                 LAR : Out   std_logic;\r
             SERR_CHECK : Out   std_logic );\r
   end component;\r
\r
begin\r
\r
   DEVSELn <= DEVSELn_DUMMY;\r
\r
   I1 : CONT_FSM\r
      Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,\r
                 FIFO_READ=>READ_FIFO, IO_READ=>IO_READ,\r
                 IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,\r
                 PCI_RSTn=>PCI_RSTn, DEVSELn=>DEVSELn_DUMMY,\r
                 FIFO_RDn=>FIFO_RDn, OE_PCI_PAR=>OE_PCI_PAR,\r
                 OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,\r
                 PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,\r
                 PERR_CHECK=>PERR_CHECK, READ=>READ, TRDYn=>TRDYn );\r
   I2 : COMM_FSM\r
      Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,\r
                 DEVSELn=>DEVSELn_DUMMY, IO_READ=>IO_READ,\r
                 IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,\r
                 PCI_RSTn=>PCI_RSTn, CF_RD_COM=>CF_RD_COM,\r
                 CF_WR_COM=>CF_WR_COM, IO_RD_COM=>IO_RD_COM,\r
                 IO_WR_COM=>IO_WR_COM );\r
   I3 : COMM_DEC\r
      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
                 IO_SPACE=>IO_SPACE, MY_ADDR=>MY_ADDR,\r
                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
                 CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,\r
                 IO_READ=>IO_READ, IO_WRITE=>IO_WRITE, LAR=>LAR,\r
                 SERR_CHECK=>SERR_CHECK );\r
\r
end SCHEMATIC;\r
Commit	Line	Data
377c0242	1	-- VHDL model created from schematic steuerung.sch -- Jan 09 09:34:14 2007\r
	2	\r
	3	-- LIBRARY vanmacro;\r
	4	-- USE vanmacro.components.ALL;\r
	5	LIBRARY ieee;\r
	6	--LIBRARY generics;\r
	7	USE ieee.std_logic_1164.ALL;\r
	8	USE ieee.numeric_std.ALL;\r
	9	--USE generics.components.ALL;\r
	10	\r
	11	entity STEUERUNG is\r
	12	Port ( AD_REG : In std_logic_vector (31 downto 0);\r
	13	CBE_REGn : In std_logic_vector (3 downto 0);\r
	14	FRAME_REGn : In std_logic;\r
	15	IDSEL_REG : In std_logic;\r
	16	IO_SPACE : In std_logic;\r
	17	MY_ADDR : In std_logic;\r
	18	PCI_CLOCK : In std_logic;\r
	19	PCI_RSTn : In std_logic;\r
	20	READ_FIFO : In std_logic;\r
	21	CF_RD_COM : Out std_logic;\r
	22	CF_WR_COM : Out std_logic;\r
	23	DEVSELn : Out std_logic;\r
	24	FIFO_RDn : Out std_logic;\r
	25	IO_RD_COM : Out std_logic;\r
	26	IO_WR_COM : Out std_logic;\r
	27	LAR : Out std_logic;\r
	28	OE_PCI_PAR : Out std_logic;\r
	29	OE_PCI_PERR : Out std_logic;\r
	30	PCI_DEVSELn : Out std_logic;\r
	31	PCI_STOPn : Out std_logic;\r
	32	PCI_TRDYn : Out std_logic;\r
	33	PERR_CHECK : Out std_logic;\r
	34	READ : Out std_logic;\r
	35	SERR_CHECK : Out std_logic;\r
	36	TRDYn : Out std_logic );\r
	37	end STEUERUNG;\r
	38	\r
	39	architecture SCHEMATIC of STEUERUNG is\r
	40	\r
	41	SIGNAL gnd : std_logic := '0';\r
	42	SIGNAL vcc : std_logic := '1';\r
	43	\r
	44	signal DEVSELn_DUMMY : std_logic;\r
	45	signal IO_READ : std_logic;\r
	46	signal IO_WRITE : std_logic;\r
	47	signal CONF_READ : std_logic;\r
	48	signal CONF_WRITE : std_logic;\r
	49	\r
	50	component CONT_FSM\r
	51	Port ( CONF_READ : In std_logic;\r
	52	CONF_WRITE : In std_logic;\r
	53	FIFO_READ : In std_logic;\r
	54	IO_READ : In std_logic;\r
	55	IO_WRITE : In std_logic;\r
	56	PCI_CLOCK : In std_logic;\r
	57	PCI_RSTn : In std_logic;\r
	58	DEVSELn : Out std_logic;\r
	59	FIFO_RDn : Out std_logic;\r
	60	OE_PCI_PAR : Out std_logic;\r
	61	OE_PCI_PERR : Out std_logic;\r
	62	PCI_DEVSELn : Out std_logic;\r
	63	PCI_STOPn : Out std_logic;\r
	64	PCI_TRDYn : Out std_logic;\r
65	PERR_CHECK : Out std_logic;\r
66	READ : Out std_logic;\r
67	TRDYn : Out std_logic );\r
68	end component;\r
69	\r
70	component COMM_FSM\r
71	Port ( CONF_READ : In std_logic;\r
72	CONF_WRITE : In std_logic;\r
73	DEVSELn : In std_logic;\r
74	IO_READ : In std_logic;\r
75	IO_WRITE : In std_logic;\r
76	PCI_CLOCK : In std_logic;\r
77	PCI_RSTn : In std_logic;\r
78	CF_RD_COM : Out std_logic;\r
79	CF_WR_COM : Out std_logic;\r
80	IO_RD_COM : Out std_logic;\r
81	IO_WR_COM : Out std_logic );\r
82	end component;\r
83	\r
84	component COMM_DEC\r
85	Port ( AD_REG : In std_logic_vector (31 downto 0);\r
86	CBE_REGn : In std_logic_vector (3 downto 0);\r
87	FRAME_REGn : In std_logic;\r
88	IDSEL_REG : In std_logic;\r
89	IO_SPACE : In std_logic;\r
90	MY_ADDR : In std_logic;\r
91	PCI_CLOCK : In std_logic;\r
92	PCI_RSTn : In std_logic;\r
93	CONF_READ : Out std_logic;\r
94	CONF_WRITE : Out std_logic;\r
95	IO_READ : Out std_logic;\r
96	IO_WRITE : Out std_logic;\r
97	LAR : Out std_logic;\r
98	SERR_CHECK : Out std_logic );\r
99	end component;\r
100	\r
101	begin\r
102	\r
103	DEVSELn <= DEVSELn_DUMMY;\r
104	\r
105	I1 : CONT_FSM\r
106	Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,\r
107	FIFO_READ=>READ_FIFO, IO_READ=>IO_READ,\r
108	IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,\r
109	PCI_RSTn=>PCI_RSTn, DEVSELn=>DEVSELn_DUMMY,\r
110	FIFO_RDn=>FIFO_RDn, OE_PCI_PAR=>OE_PCI_PAR,\r
111	OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,\r
112	PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,\r
113	PERR_CHECK=>PERR_CHECK, READ=>READ, TRDYn=>TRDYn );\r
114	I2 : COMM_FSM\r
115	Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,\r
116	DEVSELn=>DEVSELn_DUMMY, IO_READ=>IO_READ,\r
117	IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,\r
118	PCI_RSTn=>PCI_RSTn, CF_RD_COM=>CF_RD_COM,\r
119	CF_WR_COM=>CF_WR_COM, IO_RD_COM=>IO_RD_COM,\r
120	IO_WR_COM=>IO_WR_COM );\r
121	I3 : COMM_DEC\r
122	Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
123	CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
124	FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
125	IO_SPACE=>IO_SPACE, MY_ADDR=>MY_ADDR,\r
126	PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
127	CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,\r
128	IO_READ=>IO_READ, IO_WRITE=>IO_WRITE, LAR=>LAR,\r
129	SERR_CHECK=>SERR_CHECK );\r
130	\r
131	end SCHEMATIC;\r