[raggedstone] / dhwk_old / source / new_pci32tlite.vhd

--+-------------------------------------------------------------------------------------------------+\r
--|																									|\r
--|  File:			pci32tlite.vhd                       		                                   	|\r
--|																									|\r
--|  Components:	pcidec_new.vhd																		|\r
--|		            pciwbsequ.vhd           														|\r
--|		            pcidmux.vhd           															|\r
--|		            pciregs.vhd           															|\r
--|		            pcipargen.vhd          															|\r
--|		            -- Libs --             															|\r
--|		            ona.vhd		          															|\r
--|																									|\r
--|	 Description:	TARGET PCI :						 							|\r
--| 				 																				|\r
--|					* PCI Target 32 Bits															|\r
--|					* BAR0 32MByte address space													|\r
--|					* Whisbone compatible: D16, 32MB address space                                  |\r
--|																									|\r
--+-------------------------------------------------------------------------------------------------+\r
--|																									|\r
--|  Revision history :																				|\r
--|  Date 		  Version	Author	Description														|\r
--|  2005-05-13   R00A00	PAU		First alfa revision (eng)										|\r
--|	 2006-01-05   R00B00    MS      inverted reset nres 											|\r
--|                                 and added debug signals debug_init and debug_access             |																								|\r
--|																									|\r
--|  To do:																 							|\r
--|																									|\r
--+-------------------------------------------------------------------------------------------------+\r
--+-----------------------------------------------------------------+\r
--| 																|\r
--|  Copyright (C) 2005 Peio Azkarate, peio@opencores.org   		| \r
--| 																|\r
--|  This source file may be used and distributed without     		|\r
--|  restriction provided that this copyright statement is not		|\r
--|  removed from the file and that any derivative work contains	|\r
--|  the original copyright notice and the associated disclaimer.	|\r
--|                                                              	|\r
--|  This source file is free software; you can redistribute it     |\r
--|  and/or modify it under the terms of the GNU Lesser General     |\r
--|  Public License as published by the Free Software Foundation;   |\r
--|  either version 2.1 of the License, or (at your option) any     |\r
--|  later version.                                                 |\r
--| 																|\r
--|  This source is distributed in the hope that it will be         |\r
--|  useful, but WITHOUT ANY WARRANTY; without even the implied     |\r
--|  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR        |\r
--|  PURPOSE.  See the GNU Lesser General Public License for more   |\r
--|  details.                                                       |\r
--| 																|\r
--|  You should have received a copy of the GNU Lesser General      |\r
--|  Public License along with this source; if not, download it     |\r
--|  from http://www.opencores.org/lgpl.shtml                       |\r
--| 																|\r
--+-----------------------------------------------------------------+ \r
\r
--+-----------------------------------------------------------------------------+\r
--|									LIBRARIES									|\r
--+-----------------------------------------------------------------------------+\r
\r
library ieee;\r
use ieee.std_logic_1164.all;\r
\r
--+-----------------------------------------------------------------------------+\r
--|									ENTITY   									|\r
--+-----------------------------------------------------------------------------+\r
\r
entity pci32tlite is\r
generic (\r
\r
	vendorID 		: std_logic_vector(15 downto 0) := x"10EE";\r
	deviceID 		: std_logic_vector(15 downto 0) := x"0100";\r
	revisionID 		: std_logic_vector(7 downto 0) 	:= x"37";\r
	subsystemID 	: std_logic_vector(15 downto 0) := x"1558";\r
   	subsystemvID 	: std_logic_vector(15 downto 0) := x"0480";\r
		jcarr1ID 		: std_logic_vector(31 downto 0) := x"12345671";\r
		jcarr2ID 		: std_logic_vector(31 downto 0) := x"12345672";\r
		jcarr3ID 		: std_logic_vector(31 downto 0) := x"12345673";\r
		jcarr4ID 		: std_logic_vector(31 downto 0) := x"12345674";\r
		jcarr5ID 		: std_logic_vector(31 downto 0) := x"12345675";\r
		jcarr6ID 		: std_logic_vector(31 downto 0) := x"12345676";\r
		jcarr7ID 		: std_logic_vector(31 downto 0) := x"12345677";\r
		jcarr8ID 		: std_logic_vector(31 downto 0) := x"12345678";\r
		jcarr9ID 		: std_logic_vector(31 downto 0) := x"12345679";\r
		jcarr10ID 		: std_logic_vector(31 downto 0) := x"12345680";\r
		jcarr11ID 		: std_logic_vector(31 downto 0) := x"12345681";\r
		jcarr12ID 		: std_logic_vector(31 downto 0) := x"12345682";\r
		jcarr13ID 		: std_logic_vector(31 downto 0) := x"12345683";\r
		jcarr14ID 		: std_logic_vector(31 downto 0) := x"12345684";\r
		jcarr15ID 		: std_logic_vector(31 downto 0) := x"12345685";\r
		jcarr16ID 		: std_logic_vector(31 downto 0) := x"12345686";\r
		jcarr17ID 		: std_logic_vector(31 downto 0) := x"12345687";\r
		jcarr18ID 		: std_logic_vector(31 downto 0) := x"12345688";\r
		jcarr19ID 		: std_logic_vector(31 downto 0) := x"12345689";\r
		jcarr20ID 		: std_logic_vector(31 downto 0) := x"12345690";\r
		jcarr21ID 		: std_logic_vector(31 downto 0) := x"12345691";\r
		jcarr22ID 		: std_logic_vector(31 downto 0) := x"12345692";\r
		jcarr23ID 		: std_logic_vector(31 downto 0) := x"12345693";\r
		jcarr24ID 		: std_logic_vector(31 downto 0) := x"12345694";\r
		jcarr25ID 		: std_logic_vector(31 downto 0) := x"12345695";\r
		jcarr26ID 		: std_logic_vector(31 downto 0) := x"12345696";\r
		jcarr27ID 		: std_logic_vector(31 downto 0) := x"12345697";\r
		jcarr28ID 		: std_logic_vector(31 downto 0) := x"12345698";\r
		jcarr29ID 		: std_logic_vector(31 downto 0) := x"12345699";\r
		jcarr30ID 		: std_logic_vector(31 downto 0) := x"12345700";\r
		jcarr31ID 		: std_logic_vector(31 downto 0) := x"12345701";\r
		jcarr32ID 		: std_logic_vector(31 downto 0) := x"12345702";\r
		jcarr33ID 		: std_logic_vector(31 downto 0) := x"12345703";\r
		jcarr34ID 		: std_logic_vector(31 downto 0) := x"12345704";\r
		jcarr35ID 		: std_logic_vector(31 downto 0) := x"12345705";\r
		jcarr36ID 		: std_logic_vector(31 downto 0) := x"12345706";\r
		jcarr37ID 		: std_logic_vector(31 downto 0) := x"12345707";\r
		jcarr38ID 		: std_logic_vector(31 downto 0) := x"12345708";\r
		jcarr39ID 		: std_logic_vector(31 downto 0) := x"12345709";\r
		jcarr40ID 		: std_logic_vector(31 downto 0) := x"12345710";\r
		jcarr41ID 		: std_logic_vector(31 downto 0) := x"12345711";\r
		jcarr42ID 		: std_logic_vector(31 downto 0) := x"12345712"\r
\r
);\r
port (\r
\r
    -- General \r
    clk33       : in std_logic;\r
    nrst	    : in std_logic;\r
    \r
    -- PCI target 32bits\r
    ad          : inout std_logic_vector(31 downto 0);\r
    cbe         : in std_logic_vector(3 downto 0);\r
    par         : out std_logic;  \r
    frame       : in std_logic;\r
    irdy        : in std_logic;\r
    trdy        : out std_logic;\r
    devsel      : out std_logic;\r
    stop        : out std_logic;\r
    idsel       : in std_logic;\r
    perr        : out std_logic;\r
    serr        : out std_logic;\r
    intb        : out std_logic;\r
      \r
	-- Master whisbone\r
    wb_adr_o     : out std_logic_vector(24 downto 1);     \r
	wb_dat_i     : in std_logic_vector(15 downto 0);\r
    wb_dat_o     : out std_logic_vector(15 downto 0);\r
	wb_sel_o     : out std_logic_vector(1 downto 0);\r
    wb_we_o      : out std_logic;\r
	wb_stb_o     : inout std_logic;\r
	wb_cyc_o     : out std_logic;\r
	wb_ack_i     : in std_logic;\r
	wb_err_i     : in std_logic;\r
	wb_int_i     : in std_logic;\r
\r
	-- debug signals\r
	debug_init	 : out std_logic;\r
	debug_access : out std_logic \r
\r
);\r
end pci32tlite;\r
\r
\r
--+-----------------------------------------------------------------------------+\r
--|									ARCHITECTURE								|\r
--+-----------------------------------------------------------------------------+\r
\r
architecture rtl of pci32tlite is\r
\r
\r
--+-----------------------------------------------------------------------------+\r
--|									COMPONENTS									|\r
--+-----------------------------------------------------------------------------+\r
\r
\r
	component pcidec_new\r
	port (\r
	\r
	    clk_i       	: in std_logic;\r
   		nrst_i       	: in std_logic;\r
		--\r
		ad_i			: in std_logic_vector(31 downto 0);\r
		cbe_i			: in std_logic_vector(3 downto 0);\r
		idsel_i    	 	: in std_logic;\r
		bar0_i        	: in std_logic_vector(31 downto 25);\r
		memEN_i			: in std_logic;\r
		pciadrLD_i	   	: in std_logic;\r
		adrcfg_o		: out std_logic;\r
		adrmem_o		: out std_logic;\r
		adr_o			: out std_logic_vector(24 downto 1);\r
		cmd_o			: out std_logic_vector(3 downto 0)\r
		\r
	);\r
	end component;\r
\r
	\r
	component pciwbsequ\r
	port (\r
	\r
   		-- General \r
	    clk_i       	: in std_logic;\r
   		nrst_i       	: in std_logic;\r
		-- pci \r
		cmd_i			: in std_logic_vector(3 downto 0);\r
		cbe_i			: in std_logic_vector(3 downto 0);\r
		frame_i    	 	: in std_logic;\r
		irdy_i        	: in std_logic;\r
		devsel_o		: out std_logic;\r
		trdy_o        	: out std_logic;\r
		-- control\r
		adrcfg_i		: in std_logic;\r
		adrmem_i 		: in std_logic;\r
		pciadrLD_o	   	: out std_logic;\r
		pcidOE_o		: out std_logic;\r
		parOE_o			: out std_logic;		\r
		wbdatLD_o   	: out std_logic;\r
		wbrgdMX_o		: out std_logic;\r
		wbd16MX_o		: out std_logic;\r
		wrcfg_o 		: out std_logic;\r
		rdcfg_o 		: out std_logic;\r
		-- whisbone\r
		wb_sel_o		: out std_logic_vector(1 downto 0);\r
		wb_we_o			: out std_logic;\r
		wb_stb_o		: inout std_logic;	\r
		wb_cyc_o		: out std_logic;\r
		wb_ack_i		: in std_logic;\r
		wb_err_i		: in std_logic;	\r
		-- debug signals\r
		debug_init	 	: out std_logic;\r
		debug_access 	: out std_logic\r
	);\r
	end component;\r
\r
\r
	component pcidmux\r
	port (\r
	\r
	    clk_i       	: in std_logic;\r
   		nrst_i       	: in std_logic;\r
		--\r
		d_io			: inout std_logic_vector(31 downto 0);\r
		pcidatout_o		: out std_logic_vector(31 downto 0);\r
		pcidOE_i		: in std_logic;\r
		wbdatLD_i		: in std_logic;\r
		wbrgdMX_i		: in std_logic;\r
		wbd16MX_i		: in std_logic;\r
		wb_dat_i		: in std_logic_vector(15 downto 0);\r
		wb_dat_o		: out std_logic_vector(15 downto 0);\r
		rg_dat_i		: in std_logic_vector(31 downto 0);\r
		rg_dat_o		: out std_logic_vector(31 downto 0)\r
				\r
	);\r
	end component;\r
\r
\r
	component pciregs\r
	generic (\r
\r
		vendorID : std_logic_vector(15 downto 0);\r
		deviceID : std_logic_vector(15 downto 0);\r
		revisionID : std_logic_vector(7 downto 0);\r
		subsystemID : std_logic_vector(15 downto 0);\r
    	subsystemvID : std_logic_vector(15 downto 0);\r
		jcarr1ID 	: std_logic_vector(31 downto 0);\r
		jcarr2ID 	: std_logic_vector(31 downto 0);\r
		jcarr3ID 	: std_logic_vector(31 downto 0);\r
		jcarr4ID 	: std_logic_vector(31 downto 0);\r
		jcarr5ID 	: std_logic_vector(31 downto 0);\r
		jcarr6ID 	: std_logic_vector(31 downto 0);\r
		jcarr7ID 	: std_logic_vector(31 downto 0);\r
		jcarr8ID 	: std_logic_vector(31 downto 0);\r
		jcarr9ID 	: std_logic_vector(31 downto 0);\r
		jcarr10ID 	: std_logic_vector(31 downto 0);\r
		jcarr11ID 	: std_logic_vector(31 downto 0);\r
		jcarr12ID 	: std_logic_vector(31 downto 0);\r
		jcarr13ID 	: std_logic_vector(31 downto 0);\r
		jcarr14ID 	: std_logic_vector(31 downto 0);\r
		jcarr15ID 	: std_logic_vector(31 downto 0);\r
		jcarr16ID 	: std_logic_vector(31 downto 0);\r
		jcarr17ID 	: std_logic_vector(31 downto 0);\r
		jcarr18ID 	: std_logic_vector(31 downto 0);\r
		jcarr19ID 	: std_logic_vector(31 downto 0);\r
		jcarr20ID 	: std_logic_vector(31 downto 0);\r
		jcarr21ID 	: std_logic_vector(31 downto 0);\r
		jcarr22ID 	: std_logic_vector(31 downto 0);\r
		jcarr23ID 	: std_logic_vector(31 downto 0);\r
		jcarr24ID 	: std_logic_vector(31 downto 0);\r
		jcarr25ID 	: std_logic_vector(31 downto 0);\r
		jcarr26ID 	: std_logic_vector(31 downto 0);\r
		jcarr27ID 	: std_logic_vector(31 downto 0);\r
		jcarr28ID 	: std_logic_vector(31 downto 0);\r
		jcarr29ID 	: std_logic_vector(31 downto 0);\r
		jcarr30ID 	: std_logic_vector(31 downto 0);\r
		jcarr31ID 	: std_logic_vector(31 downto 0);\r
		jcarr32ID 	: std_logic_vector(31 downto 0);\r
		jcarr33ID 	: std_logic_vector(31 downto 0);\r
		jcarr34ID 	: std_logic_vector(31 downto 0);\r
		jcarr35ID 	: std_logic_vector(31 downto 0);\r
		jcarr36ID 	: std_logic_vector(31 downto 0);\r
		jcarr37ID 	: std_logic_vector(31 downto 0);\r
		jcarr38ID 	: std_logic_vector(31 downto 0);\r
		jcarr39ID 	: std_logic_vector(31 downto 0);\r
		jcarr40ID 	: std_logic_vector(31 downto 0);\r
		jcarr41ID 	: std_logic_vector(31 downto 0);\r
		jcarr42ID 	: std_logic_vector(31 downto 0)\r
\r
	);\r
	port (\r
	\r
	    clk_i       	: in std_logic;\r
   		nrst_i       	: in std_logic;\r
		--\r
		adr_i			: in std_logic_vector(7 downto 2);\r
		cbe_i			: in std_logic_vector(3 downto 0);\r
		dat_i			: in std_logic_vector(31 downto 0);\r
		dat_o			: out std_logic_vector(31 downto 0);\r
   		wrcfg_i       	: in std_logic;\r
   		rdcfg_i       	: in std_logic;\r
   		perr_i       	: in std_logic;\r
   		serr_i       	: in std_logic;\r
   		tabort_i       	: in std_logic;\r
		bar0_o			: out std_logic_vector(31 downto 25);\r
		perrEN_o		: out std_logic;\r
		serrEN_o		: out std_logic;\r
		memEN_o			: out std_logic\r
				\r
	);\r
	end component;\r
\r
\r
	component pcipargen\r
	port (\r
\r
		clk_i			: in std_logic;\r
		pcidatout_i		: in std_logic_vector(31 downto 0);\r
		cbe_i			: in std_logic_vector(3 downto 0);\r
		parOE_i 		: in std_logic;\r
		par_o			: out std_logic\r
	\r
	);   \r
	end component;\r
\r
\r
--+-----------------------------------------------------------------------------+\r
--|									CONSTANTS  									|\r
--+-----------------------------------------------------------------------------+\r
--+-----------------------------------------------------------------------------+\r
--|									SIGNALS   									|\r
--+-----------------------------------------------------------------------------+\r
\r
	signal bar0			: std_logic_vector(31 downto 25);\r
	signal memEN		: std_logic;\r
	signal pciadrLD		: std_logic;\r
	signal adrcfg		: std_logic;\r
	signal adrmem		: std_logic;\r
	signal adr			: std_logic_vector(24 downto 1);\r
	signal cmd			: std_logic_vector(3 downto 0);\r
	signal pcidOE		: std_logic;\r
	signal parOE		: std_logic;	\r
	signal wbdatLD		: std_logic;\r
	signal wbrgdMX		: std_logic;\r
	signal wbd16MX		: std_logic;\r
	signal wrcfg		: std_logic;\r
	signal rdcfg		: std_logic;\r
	signal pcidatread	: std_logic_vector(31 downto 0);\r
	signal pcidatwrite	: std_logic_vector(31 downto 0);\r
	signal pcidatout	: std_logic_vector(31 downto 0);	\r
	signal parerr		: std_logic;\r
	signal syserr		: std_logic;\r
	signal tabort		: std_logic;\r
	signal perrEN		: std_logic;\r
	signal serrEN		: std_logic;\r
			\r
begin\r
\r
\r
    --+-------------------------------------------------------------------------+\r
    --|  Component instances													|\r
    --+-------------------------------------------------------------------------+\r
\r
	--+-----------------------------------------+\r
	--|  PCI decoder							|\r
	--+-----------------------------------------+\r
\r
	u1: component pcidec_new\r
	port map (\r
\r
	    clk_i   	=> clk33,\r
   		nrst_i 		=> nrst,\r
		--\r
		ad_i		=> ad,\r
		cbe_i		=> cbe,\r
		idsel_i    	=> idsel,\r
		bar0_i      => bar0,\r
		memEN_i		=> memEN,\r
		pciadrLD_i	=> pciadrLD,	\r
		adrcfg_o	=> adrcfg,\r
		adrmem_o	=> adrmem,\r
		adr_o		=> adr,\r
		cmd_o		=> cmd\r
		\r
	);\r
\r
\r
	--+-----------------------------------------+\r
	--|  PCI-WB Sequencer						|\r
	--+-----------------------------------------+\r
\r
	u2: component pciwbsequ \r
	port map (\r
\r
   		-- General \r
	    clk_i 		=> clk33,     	\r
   		nrst_i      => nrst,\r
		-- pci \r
		cmd_i			=> cmd,\r
		cbe_i			=> cbe,\r
		frame_i    		=> frame,\r
		irdy_i      	=> irdy,	\r
		devsel_o		=> devsel,\r
		trdy_o      	=> trdy, 	\r
		-- control\r
		adrcfg_i		=> adrcfg,\r
		adrmem_i 		=> adrmem,\r
		pciadrLD_o		=> pciadrLD,\r
		pcidOE_o		=> pcidOE,\r
		parOE_o			=> parOE,    \r
		wbdatLD_o   	=> wbdatLD,\r
		wbrgdMX_o		=> wbrgdMX,\r
		wbd16MX_o		=> wbd16MX,\r
		wrcfg_o 		=> wrcfg,\r
		rdcfg_o 		=> rdcfg,\r
		-- whisbone\r
		wb_sel_o		=> wb_sel_o,\r
		wb_we_o			=> wb_we_o,\r
		wb_stb_o		=> wb_stb_o,\r
		wb_cyc_o		=> wb_cyc_o,\r
		wb_ack_i		=> wb_ack_i,\r
		wb_err_i		=> wb_err_i,\r
		-- debug signals\r
		debug_init		=> debug_init, \r
		debug_access 	=> debug_access\r
	);\r
   \r
\r
	--+-----------------------------------------+\r
	--|  PCI-wb datamultiplexer					|\r
	--+-----------------------------------------+\r
\r
	u3: component pcidmux\r
	port map (\r
\r
	    clk_i   	=> clk33,\r
   		nrst_i  	=> nrst,\r
		--\r
		d_io		=> ad,	\r
		pcidatout_o	=> pcidatout,	\r
		pcidOE_i	=> pcidOE,\r
		wbdatLD_i	=> wbdatLD,\r
		wbrgdMX_i	=> wbrgdMX,\r
		wbd16MX_i	=> wbd16MX,\r
		wb_dat_i	=> wb_dat_i,\r
		wb_dat_o	=> wb_dat_o,\r
		rg_dat_i	=> pcidatread,\r
		rg_dat_o	=> pcidatwrite\r
			\r
	);\r
\r
\r
	--+-----------------------------------------+\r
	--|  PCI registers							|\r
	--+-----------------------------------------+\r
\r
	u4: component pciregs\r
	generic map (\r
\r
		vendorID 		=> vendorID,\r
		deviceID 		=> deviceID,\r
		revisionID 		=> revisionID,\r
		subsystemID 	=> subsystemID,\r
    	subsystemvID 	=> subsystemvID,\r
		jcarr1ID 	=> jcarr1ID,\r
		jcarr2ID 	=> jcarr2ID,\r
		jcarr3ID 	=> jcarr3ID,\r
		jcarr4ID 	=> jcarr4ID,\r
		jcarr5ID 	=> jcarr5ID,\r
		jcarr6ID 	=> jcarr6ID,\r
		jcarr7ID 	=> jcarr7ID,\r
		jcarr8ID 	=> jcarr8ID,\r
		jcarr9ID 	=> jcarr9ID,\r
		jcarr10ID 	=> jcarr10ID,\r
		jcarr11ID 	=> jcarr11ID,\r
		jcarr12ID 	=> jcarr12ID,\r
		jcarr13ID 	=> jcarr13ID,\r
		jcarr14ID 	=> jcarr14ID,\r
		jcarr15ID 	=> jcarr15ID,\r
		jcarr16ID 	=> jcarr16ID,\r
		jcarr17ID 	=> jcarr17ID,\r
		jcarr18ID 	=> jcarr18ID,\r
		jcarr19ID 	=> jcarr19ID,\r
		jcarr20ID 	=> jcarr20ID,\r
		jcarr21ID 	=> jcarr21ID,\r
		jcarr22ID 	=> jcarr22ID,\r
		jcarr23ID 	=> jcarr23ID,\r
		jcarr24ID 	=> jcarr24ID,\r
		jcarr25ID 	=> jcarr25ID,\r
		jcarr26ID 	=> jcarr26ID,\r
		jcarr27ID 	=> jcarr27ID,\r
		jcarr28ID 	=> jcarr28ID,\r
		jcarr29ID 	=> jcarr29ID,\r
		jcarr30ID 	=> jcarr30ID,\r
		jcarr31ID 	=> jcarr31ID,\r
		jcarr32ID 	=> jcarr32ID,\r
		jcarr33ID 	=> jcarr33ID,\r
		jcarr34ID 	=> jcarr34ID,\r
		jcarr35ID 	=> jcarr35ID,\r
		jcarr36ID 	=> jcarr36ID,\r
		jcarr37ID 	=> jcarr37ID,\r
		jcarr38ID 	=> jcarr38ID,\r
		jcarr39ID 	=> jcarr39ID,\r
		jcarr40ID 	=> jcarr40ID,\r
		jcarr41ID 	=> jcarr41ID,\r
		jcarr42ID 	=> jcarr42ID\r
\r
	)\r
	port map (\r
\r
	    clk_i   	=> clk33,\r
   		nrst_i  	=> nrst,\r
		--\r
		adr_i		=> adr(7 downto 2),\r
		cbe_i		=> cbe,\r
		dat_i		=> pcidatwrite,\r
		dat_o		=> pcidatread,\r
   		wrcfg_i     => wrcfg,\r
   		rdcfg_i     => rdcfg,\r
   		perr_i      => parerr,\r
   		serr_i      => syserr,\r
   		tabort_i    => tabort,\r
		bar0_o		=> bar0,\r
		perrEN_o	=> perrEN,\r
		serrEN_o	=> serrEN,\r
		memEN_o		=> memEN\r
					\r
	);\r
	\r
	--+-----------------------------------------+\r
	--|  PCI Parity Gnerator					|\r
	--+-----------------------------------------+\r
\r
	u5: component pcipargen\r
	port map (\r
\r
	    clk_i   	=> clk33,\r
		pcidatout_i	=> pcidatout,	\r
		cbe_i		=> cbe,\r
		parOE_i		=> parOE,	\r
		par_o		=> par\r
					\r
	);\r
\r
\r
	--+-----------------------------------------+\r
	--|  Whisbone Address bus					|\r
	--+-----------------------------------------+\r
	\r
	wb_adr_o <= adr;\r
\r
\r
	--+-----------------------------------------+\r
	--|  unimplemented							|\r
	--+-----------------------------------------+\r
\r
	parerr 	<= '0';\r
	syserr 	<= '0';\r
	tabort 	<= '0';\r
\r
\r
	--+-----------------------------------------+\r
	--|  unused outputs							|\r
	--+-----------------------------------------+\r
	-- #stop: Curret TARGET indicates to Master stop current transaction\r
	-- #perr:\r
	-- #serr:\r
	\r
	perr 	<= 'Z';\r
	serr	<= 'Z';\r
	stop	<= 'Z';\r
	intb	<= '0' when ( wb_int_i = '1' ) else 'Z';\r
\r
		\r
end rtl;\r
\r
\r
Commit	Line	Data
ebba63a9	1	--+-------------------------------------------------------------------------------------------------+\r
	2	--\| \|\r
	3	--\| File: pci32tlite.vhd \|\r
	4	--\| \|\r
	5	--\| Components: pcidec_new.vhd \|\r
	6	--\| pciwbsequ.vhd \|\r
	7	--\| pcidmux.vhd \|\r
	8	--\| pciregs.vhd \|\r
	9	--\| pcipargen.vhd \|\r
	10	--\| -- Libs -- \|\r
	11	--\| ona.vhd \|\r
	12	--\| \|\r
	13	--\| Description: TARGET PCI : \|\r
	14	--\| \|\r
	15	--\| * PCI Target 32 Bits \|\r
	16	--\| * BAR0 32MByte address space \|\r
	17	--\| * Whisbone compatible: D16, 32MB address space \|\r
	18	--\| \|\r
	19	--+-------------------------------------------------------------------------------------------------+\r
	20	--\| \|\r
	21	--\| Revision history : \|\r
	22	--\| Date Version Author Description \|\r
	23	--\| 2005-05-13 R00A00 PAU First alfa revision (eng) \|\r
	24	--\| 2006-01-05 R00B00 MS inverted reset nres \|\r
	25	--\| and added debug signals debug_init and debug_access \| \|\r
	26	--\| \|\r
	27	--\| To do: \|\r
	28	--\| \|\r
	29	--+-------------------------------------------------------------------------------------------------+\r
	30	--+-----------------------------------------------------------------+\r
	31	--\| \|\r
	32	--\| Copyright (C) 2005 Peio Azkarate, peio@opencores.org \| \r
	33	--\| \|\r
	34	--\| This source file may be used and distributed without \|\r
	35	--\| restriction provided that this copyright statement is not \|\r
	36	--\| removed from the file and that any derivative work contains \|\r
	37	--\| the original copyright notice and the associated disclaimer. \|\r
	38	--\| \|\r
	39	--\| This source file is free software; you can redistribute it \|\r
	40	--\| and/or modify it under the terms of the GNU Lesser General \|\r
	41	--\| Public License as published by the Free Software Foundation; \|\r
	42	--\| either version 2.1 of the License, or (at your option) any \|\r
	43	--\| later version. \|\r
	44	--\| \|\r
	45	--\| This source is distributed in the hope that it will be \|\r
	46	--\| useful, but WITHOUT ANY WARRANTY; without even the implied \|\r
	47	--\| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \|\r
	48	--\| PURPOSE. See the GNU Lesser General Public License for more \|\r
	49	--\| details. \|\r
	50	--\| \|\r
	51	--\| You should have received a copy of the GNU Lesser General \|\r
	52	--\| Public License along with this source; if not, download it \|\r
	53	--\| from http://www.opencores.org/lgpl.shtml \|\r
	54	--\| \|\r
	55	--+-----------------------------------------------------------------+ \r
	56	\r
	57	--+-----------------------------------------------------------------------------+\r
	58	--\| LIBRARIES \|\r
	59	--+-----------------------------------------------------------------------------+\r
	60	\r
	61	library ieee;\r
	62	use ieee.std_logic_1164.all;\r
	63	\r
	64	--+-----------------------------------------------------------------------------+\r
65	--\| ENTITY \|\r
66	--+-----------------------------------------------------------------------------+\r
67	\r
68	entity pci32tlite is\r
69	generic (\r
70	\r
71	vendorID : std_logic_vector(15 downto 0) := x"10EE";\r
72	deviceID : std_logic_vector(15 downto 0) := x"0100";\r
73	revisionID : std_logic_vector(7 downto 0) := x"37";\r
74	subsystemID : std_logic_vector(15 downto 0) := x"1558";\r
75	subsystemvID : std_logic_vector(15 downto 0) := x"0480";\r
76	jcarr1ID : std_logic_vector(31 downto 0) := x"12345671";\r
77	jcarr2ID : std_logic_vector(31 downto 0) := x"12345672";\r
78	jcarr3ID : std_logic_vector(31 downto 0) := x"12345673";\r
79	jcarr4ID : std_logic_vector(31 downto 0) := x"12345674";\r
80	jcarr5ID : std_logic_vector(31 downto 0) := x"12345675";\r
81	jcarr6ID : std_logic_vector(31 downto 0) := x"12345676";\r
82	jcarr7ID : std_logic_vector(31 downto 0) := x"12345677";\r
83	jcarr8ID : std_logic_vector(31 downto 0) := x"12345678";\r
84	jcarr9ID : std_logic_vector(31 downto 0) := x"12345679";\r
85	jcarr10ID : std_logic_vector(31 downto 0) := x"12345680";\r
86	jcarr11ID : std_logic_vector(31 downto 0) := x"12345681";\r
87	jcarr12ID : std_logic_vector(31 downto 0) := x"12345682";\r
88	jcarr13ID : std_logic_vector(31 downto 0) := x"12345683";\r
89	jcarr14ID : std_logic_vector(31 downto 0) := x"12345684";\r
90	jcarr15ID : std_logic_vector(31 downto 0) := x"12345685";\r
91	jcarr16ID : std_logic_vector(31 downto 0) := x"12345686";\r
92	jcarr17ID : std_logic_vector(31 downto 0) := x"12345687";\r
93	jcarr18ID : std_logic_vector(31 downto 0) := x"12345688";\r
94	jcarr19ID : std_logic_vector(31 downto 0) := x"12345689";\r
95	jcarr20ID : std_logic_vector(31 downto 0) := x"12345690";\r
96	jcarr21ID : std_logic_vector(31 downto 0) := x"12345691";\r
97	jcarr22ID : std_logic_vector(31 downto 0) := x"12345692";\r
98	jcarr23ID : std_logic_vector(31 downto 0) := x"12345693";\r
99	jcarr24ID : std_logic_vector(31 downto 0) := x"12345694";\r
100	jcarr25ID : std_logic_vector(31 downto 0) := x"12345695";\r
101	jcarr26ID : std_logic_vector(31 downto 0) := x"12345696";\r
102	jcarr27ID : std_logic_vector(31 downto 0) := x"12345697";\r
103	jcarr28ID : std_logic_vector(31 downto 0) := x"12345698";\r
104	jcarr29ID : std_logic_vector(31 downto 0) := x"12345699";\r
105	jcarr30ID : std_logic_vector(31 downto 0) := x"12345700";\r
106	jcarr31ID : std_logic_vector(31 downto 0) := x"12345701";\r
107	jcarr32ID : std_logic_vector(31 downto 0) := x"12345702";\r
108	jcarr33ID : std_logic_vector(31 downto 0) := x"12345703";\r
109	jcarr34ID : std_logic_vector(31 downto 0) := x"12345704";\r
110	jcarr35ID : std_logic_vector(31 downto 0) := x"12345705";\r
111	jcarr36ID : std_logic_vector(31 downto 0) := x"12345706";\r
112	jcarr37ID : std_logic_vector(31 downto 0) := x"12345707";\r
113	jcarr38ID : std_logic_vector(31 downto 0) := x"12345708";\r
114	jcarr39ID : std_logic_vector(31 downto 0) := x"12345709";\r
115	jcarr40ID : std_logic_vector(31 downto 0) := x"12345710";\r
116	jcarr41ID : std_logic_vector(31 downto 0) := x"12345711";\r
117	jcarr42ID : std_logic_vector(31 downto 0) := x"12345712"\r
118	\r
119	);\r
120	port (\r
121	\r
122	-- General \r
123	clk33 : in std_logic;\r
124	nrst : in std_logic;\r
125	\r
126	-- PCI target 32bits\r
127	ad : inout std_logic_vector(31 downto 0);\r
128	cbe : in std_logic_vector(3 downto 0);\r
129	par : out std_logic; \r
130	frame : in std_logic;\r
131	irdy : in std_logic;\r
132	trdy : out std_logic;\r
133	devsel : out std_logic;\r
134	stop : out std_logic;\r
135	idsel : in std_logic;\r
136	perr : out std_logic;\r
137	serr : out std_logic;\r
138	intb : out std_logic;\r
139	\r
140	-- Master whisbone\r
141	wb_adr_o : out std_logic_vector(24 downto 1); \r
142	wb_dat_i : in std_logic_vector(15 downto 0);\r
143	wb_dat_o : out std_logic_vector(15 downto 0);\r
144	wb_sel_o : out std_logic_vector(1 downto 0);\r
145	wb_we_o : out std_logic;\r
146	wb_stb_o : inout std_logic;\r
147	wb_cyc_o : out std_logic;\r
148	wb_ack_i : in std_logic;\r
149	wb_err_i : in std_logic;\r
150	wb_int_i : in std_logic;\r
151	\r
152	-- debug signals\r
153	debug_init : out std_logic;\r
154	debug_access : out std_logic \r
155	\r
156	);\r
157	end pci32tlite;\r
158	\r
159	\r
160	--+-----------------------------------------------------------------------------+\r
161	--\| ARCHITECTURE \|\r
162	--+-----------------------------------------------------------------------------+\r
163	\r
164	architecture rtl of pci32tlite is\r
165	\r
166	\r
167	--+-----------------------------------------------------------------------------+\r
168	--\| COMPONENTS \|\r
169	--+-----------------------------------------------------------------------------+\r
170	\r
171	\r
172	component pcidec_new\r
173	port (\r
174	\r
175	clk_i : in std_logic;\r
176	nrst_i : in std_logic;\r
177	--\r
178	ad_i : in std_logic_vector(31 downto 0);\r
179	cbe_i : in std_logic_vector(3 downto 0);\r
180	idsel_i : in std_logic;\r
181	bar0_i : in std_logic_vector(31 downto 25);\r
182	memEN_i : in std_logic;\r
183	pciadrLD_i : in std_logic;\r
184	adrcfg_o : out std_logic;\r
185	adrmem_o : out std_logic;\r
186	adr_o : out std_logic_vector(24 downto 1);\r
187	cmd_o : out std_logic_vector(3 downto 0)\r
188	\r
189	);\r
190	end component;\r
191	\r
192	\r
193	component pciwbsequ\r
194	port (\r
195	\r
196	-- General \r
197	clk_i : in std_logic;\r
198	nrst_i : in std_logic;\r
199	-- pci \r
200	cmd_i : in std_logic_vector(3 downto 0);\r
201	cbe_i : in std_logic_vector(3 downto 0);\r
202	frame_i : in std_logic;\r
203	irdy_i : in std_logic;\r
204	devsel_o : out std_logic;\r
205	trdy_o : out std_logic;\r
206	-- control\r
207	adrcfg_i : in std_logic;\r
208	adrmem_i : in std_logic;\r
209	pciadrLD_o : out std_logic;\r
210	pcidOE_o : out std_logic;\r
211	parOE_o : out std_logic; \r
212	wbdatLD_o : out std_logic;\r
213	wbrgdMX_o : out std_logic;\r
214	wbd16MX_o : out std_logic;\r
215	wrcfg_o : out std_logic;\r
216	rdcfg_o : out std_logic;\r
217	-- whisbone\r
218	wb_sel_o : out std_logic_vector(1 downto 0);\r
219	wb_we_o : out std_logic;\r
220	wb_stb_o : inout std_logic; \r
221	wb_cyc_o : out std_logic;\r
222	wb_ack_i : in std_logic;\r
223	wb_err_i : in std_logic; \r
224	-- debug signals\r
225	debug_init : out std_logic;\r
226	debug_access : out std_logic\r
227	);\r
228	end component;\r
229	\r
230	\r
231	component pcidmux\r
232	port (\r
233	\r
234	clk_i : in std_logic;\r
235	nrst_i : in std_logic;\r
236	--\r
237	d_io : inout std_logic_vector(31 downto 0);\r
238	pcidatout_o : out std_logic_vector(31 downto 0);\r
239	pcidOE_i : in std_logic;\r
240	wbdatLD_i : in std_logic;\r
241	wbrgdMX_i : in std_logic;\r
242	wbd16MX_i : in std_logic;\r
243	wb_dat_i : in std_logic_vector(15 downto 0);\r
244	wb_dat_o : out std_logic_vector(15 downto 0);\r
245	rg_dat_i : in std_logic_vector(31 downto 0);\r
246	rg_dat_o : out std_logic_vector(31 downto 0)\r
247	\r
248	);\r
249	end component;\r
250	\r
251	\r
252	component pciregs\r
253	generic (\r
254	\r
255	vendorID : std_logic_vector(15 downto 0);\r
256	deviceID : std_logic_vector(15 downto 0);\r
257	revisionID : std_logic_vector(7 downto 0);\r
258	subsystemID : std_logic_vector(15 downto 0);\r
259	subsystemvID : std_logic_vector(15 downto 0);\r
260	jcarr1ID : std_logic_vector(31 downto 0);\r
261	jcarr2ID : std_logic_vector(31 downto 0);\r
262	jcarr3ID : std_logic_vector(31 downto 0);\r
263	jcarr4ID : std_logic_vector(31 downto 0);\r
264	jcarr5ID : std_logic_vector(31 downto 0);\r
265	jcarr6ID : std_logic_vector(31 downto 0);\r
266	jcarr7ID : std_logic_vector(31 downto 0);\r
267	jcarr8ID : std_logic_vector(31 downto 0);\r
268	jcarr9ID : std_logic_vector(31 downto 0);\r
269	jcarr10ID : std_logic_vector(31 downto 0);\r
270	jcarr11ID : std_logic_vector(31 downto 0);\r
271	jcarr12ID : std_logic_vector(31 downto 0);\r
272	jcarr13ID : std_logic_vector(31 downto 0);\r
273	jcarr14ID : std_logic_vector(31 downto 0);\r
274	jcarr15ID : std_logic_vector(31 downto 0);\r
275	jcarr16ID : std_logic_vector(31 downto 0);\r
276	jcarr17ID : std_logic_vector(31 downto 0);\r
277	jcarr18ID : std_logic_vector(31 downto 0);\r
278	jcarr19ID : std_logic_vector(31 downto 0);\r
279	jcarr20ID : std_logic_vector(31 downto 0);\r
280	jcarr21ID : std_logic_vector(31 downto 0);\r
281	jcarr22ID : std_logic_vector(31 downto 0);\r
282	jcarr23ID : std_logic_vector(31 downto 0);\r
283	jcarr24ID : std_logic_vector(31 downto 0);\r
284	jcarr25ID : std_logic_vector(31 downto 0);\r
285	jcarr26ID : std_logic_vector(31 downto 0);\r
286	jcarr27ID : std_logic_vector(31 downto 0);\r
287	jcarr28ID : std_logic_vector(31 downto 0);\r
288	jcarr29ID : std_logic_vector(31 downto 0);\r
289	jcarr30ID : std_logic_vector(31 downto 0);\r
290	jcarr31ID : std_logic_vector(31 downto 0);\r
291	jcarr32ID : std_logic_vector(31 downto 0);\r
292	jcarr33ID : std_logic_vector(31 downto 0);\r
293	jcarr34ID : std_logic_vector(31 downto 0);\r
294	jcarr35ID : std_logic_vector(31 downto 0);\r
295	jcarr36ID : std_logic_vector(31 downto 0);\r
296	jcarr37ID : std_logic_vector(31 downto 0);\r
297	jcarr38ID : std_logic_vector(31 downto 0);\r
298	jcarr39ID : std_logic_vector(31 downto 0);\r
299	jcarr40ID : std_logic_vector(31 downto 0);\r
300	jcarr41ID : std_logic_vector(31 downto 0);\r
301	jcarr42ID : std_logic_vector(31 downto 0)\r
302	\r
303	);\r
304	port (\r
305	\r
306	clk_i : in std_logic;\r
307	nrst_i : in std_logic;\r
308	--\r
309	adr_i : in std_logic_vector(7 downto 2);\r
310	cbe_i : in std_logic_vector(3 downto 0);\r
311	dat_i : in std_logic_vector(31 downto 0);\r
312	dat_o : out std_logic_vector(31 downto 0);\r
313	wrcfg_i : in std_logic;\r
314	rdcfg_i : in std_logic;\r
315	perr_i : in std_logic;\r
316	serr_i : in std_logic;\r
317	tabort_i : in std_logic;\r
318	bar0_o : out std_logic_vector(31 downto 25);\r
319	perrEN_o : out std_logic;\r
320	serrEN_o : out std_logic;\r
321	memEN_o : out std_logic\r
322	\r
323	);\r
324	end component;\r
325	\r
326	\r
327	component pcipargen\r
328	port (\r
329	\r
330	clk_i : in std_logic;\r
331	pcidatout_i : in std_logic_vector(31 downto 0);\r
332	cbe_i : in std_logic_vector(3 downto 0);\r
333	parOE_i : in std_logic;\r
334	par_o : out std_logic\r
335	\r
336	); \r
337	end component;\r
338	\r
339	\r
340	--+-----------------------------------------------------------------------------+\r
341	--\| CONSTANTS \|\r
342	--+-----------------------------------------------------------------------------+\r
343	--+-----------------------------------------------------------------------------+\r
344	--\| SIGNALS \|\r
345	--+-----------------------------------------------------------------------------+\r
346	\r
347	signal bar0 : std_logic_vector(31 downto 25);\r
348	signal memEN : std_logic;\r
349	signal pciadrLD : std_logic;\r
350	signal adrcfg : std_logic;\r
351	signal adrmem : std_logic;\r
352	signal adr : std_logic_vector(24 downto 1);\r
353	signal cmd : std_logic_vector(3 downto 0);\r
354	signal pcidOE : std_logic;\r
355	signal parOE : std_logic; \r
356	signal wbdatLD : std_logic;\r
357	signal wbrgdMX : std_logic;\r
358	signal wbd16MX : std_logic;\r
359	signal wrcfg : std_logic;\r
360	signal rdcfg : std_logic;\r
361	signal pcidatread : std_logic_vector(31 downto 0);\r
362	signal pcidatwrite : std_logic_vector(31 downto 0);\r
363	signal pcidatout : std_logic_vector(31 downto 0); \r
364	signal parerr : std_logic;\r
365	signal syserr : std_logic;\r
366	signal tabort : std_logic;\r
367	signal perrEN : std_logic;\r
368	signal serrEN : std_logic;\r
369	\r
370	begin\r
371	\r
372	\r
373	--+-------------------------------------------------------------------------+\r
374	--\| Component instances \|\r
375	--+-------------------------------------------------------------------------+\r
376	\r
377	--+-----------------------------------------+\r
378	--\| PCI decoder \|\r
379	--+-----------------------------------------+\r
380	\r
381	u1: component pcidec_new\r
382	port map (\r
383	\r
384	clk_i => clk33,\r
385	nrst_i => nrst,\r
386	--\r
387	ad_i => ad,\r
388	cbe_i => cbe,\r
389	idsel_i => idsel,\r
390	bar0_i => bar0,\r
391	memEN_i => memEN,\r
392	pciadrLD_i => pciadrLD, \r
393	adrcfg_o => adrcfg,\r
394	adrmem_o => adrmem,\r
395	adr_o => adr,\r
396	cmd_o => cmd\r
397	\r
398	);\r
399	\r
400	\r
401	--+-----------------------------------------+\r
402	--\| PCI-WB Sequencer \|\r
403	--+-----------------------------------------+\r
404	\r
405	u2: component pciwbsequ \r
406	port map (\r
407	\r
408	-- General \r
409	clk_i => clk33, \r
410	nrst_i => nrst,\r
411	-- pci \r
412	cmd_i => cmd,\r
413	cbe_i => cbe,\r
414	frame_i => frame,\r
415	irdy_i => irdy, \r
416	devsel_o => devsel,\r
417	trdy_o => trdy, \r
418	-- control\r
419	adrcfg_i => adrcfg,\r
420	adrmem_i => adrmem,\r
421	pciadrLD_o => pciadrLD,\r
422	pcidOE_o => pcidOE,\r
423	parOE_o => parOE, \r
424	wbdatLD_o => wbdatLD,\r
425	wbrgdMX_o => wbrgdMX,\r
426	wbd16MX_o => wbd16MX,\r
427	wrcfg_o => wrcfg,\r
428	rdcfg_o => rdcfg,\r
429	-- whisbone\r
430	wb_sel_o => wb_sel_o,\r
431	wb_we_o => wb_we_o,\r
432	wb_stb_o => wb_stb_o,\r
433	wb_cyc_o => wb_cyc_o,\r
434	wb_ack_i => wb_ack_i,\r
435	wb_err_i => wb_err_i,\r
436	-- debug signals\r
437	debug_init => debug_init, \r
438	debug_access => debug_access\r
439	);\r
440	\r
441	\r
442	--+-----------------------------------------+\r
443	--\| PCI-wb datamultiplexer \|\r
444	--+-----------------------------------------+\r
445	\r
446	u3: component pcidmux\r
447	port map (\r
448	\r
449	clk_i => clk33,\r
450	nrst_i => nrst,\r
451	--\r
452	d_io => ad, \r
453	pcidatout_o => pcidatout, \r
454	pcidOE_i => pcidOE,\r
455	wbdatLD_i => wbdatLD,\r
456	wbrgdMX_i => wbrgdMX,\r
457	wbd16MX_i => wbd16MX,\r
458	wb_dat_i => wb_dat_i,\r
459	wb_dat_o => wb_dat_o,\r
460	rg_dat_i => pcidatread,\r
461	rg_dat_o => pcidatwrite\r
462	\r
463	);\r
464	\r
465	\r
466	--+-----------------------------------------+\r
467	--\| PCI registers \|\r
468	--+-----------------------------------------+\r
469	\r
470	u4: component pciregs\r
471	generic map (\r
472	\r
473	vendorID => vendorID,\r
474	deviceID => deviceID,\r
475	revisionID => revisionID,\r
476	subsystemID => subsystemID,\r
477	subsystemvID => subsystemvID,\r
478	jcarr1ID => jcarr1ID,\r
479	jcarr2ID => jcarr2ID,\r
480	jcarr3ID => jcarr3ID,\r
481	jcarr4ID => jcarr4ID,\r
482	jcarr5ID => jcarr5ID,\r
483	jcarr6ID => jcarr6ID,\r
484	jcarr7ID => jcarr7ID,\r
485	jcarr8ID => jcarr8ID,\r
486	jcarr9ID => jcarr9ID,\r
487	jcarr10ID => jcarr10ID,\r
488	jcarr11ID => jcarr11ID,\r
489	jcarr12ID => jcarr12ID,\r
490	jcarr13ID => jcarr13ID,\r
491	jcarr14ID => jcarr14ID,\r
492	jcarr15ID => jcarr15ID,\r
493	jcarr16ID => jcarr16ID,\r
494	jcarr17ID => jcarr17ID,\r
495	jcarr18ID => jcarr18ID,\r
496	jcarr19ID => jcarr19ID,\r
497	jcarr20ID => jcarr20ID,\r
498	jcarr21ID => jcarr21ID,\r
499	jcarr22ID => jcarr22ID,\r
500	jcarr23ID => jcarr23ID,\r
501	jcarr24ID => jcarr24ID,\r
502	jcarr25ID => jcarr25ID,\r
503	jcarr26ID => jcarr26ID,\r
504	jcarr27ID => jcarr27ID,\r
505	jcarr28ID => jcarr28ID,\r
506	jcarr29ID => jcarr29ID,\r
507	jcarr30ID => jcarr30ID,\r
508	jcarr31ID => jcarr31ID,\r
509	jcarr32ID => jcarr32ID,\r
510	jcarr33ID => jcarr33ID,\r
511	jcarr34ID => jcarr34ID,\r
512	jcarr35ID => jcarr35ID,\r
513	jcarr36ID => jcarr36ID,\r
514	jcarr37ID => jcarr37ID,\r
515	jcarr38ID => jcarr38ID,\r
516	jcarr39ID => jcarr39ID,\r
517	jcarr40ID => jcarr40ID,\r
518	jcarr41ID => jcarr41ID,\r
519	jcarr42ID => jcarr42ID\r
520	\r
521	)\r
522	port map (\r
523	\r
524	clk_i => clk33,\r
525	nrst_i => nrst,\r
526	--\r
527	adr_i => adr(7 downto 2),\r
528	cbe_i => cbe,\r
529	dat_i => pcidatwrite,\r
530	dat_o => pcidatread,\r
531	wrcfg_i => wrcfg,\r
532	rdcfg_i => rdcfg,\r
533	perr_i => parerr,\r
534	serr_i => syserr,\r
535	tabort_i => tabort,\r
536	bar0_o => bar0,\r
537	perrEN_o => perrEN,\r
538	serrEN_o => serrEN,\r
539	memEN_o => memEN\r
540	\r
541	);\r
542	\r
543	--+-----------------------------------------+\r
544	--\| PCI Parity Gnerator \|\r
545	--+-----------------------------------------+\r
546	\r
547	u5: component pcipargen\r
548	port map (\r
549	\r
550	clk_i => clk33,\r
551	pcidatout_i => pcidatout, \r
552	cbe_i => cbe,\r
553	parOE_i => parOE, \r
554	par_o => par\r
555	\r
556	);\r
557	\r
558	\r
559	--+-----------------------------------------+\r
560	--\| Whisbone Address bus \|\r
561	--+-----------------------------------------+\r
562	\r
563	wb_adr_o <= adr;\r
564	\r
565	\r
566	--+-----------------------------------------+\r
567	--\| unimplemented \|\r
568	--+-----------------------------------------+\r
569	\r
570	parerr <= '0';\r
571	syserr <= '0';\r
572	tabort <= '0';\r
573	\r
574	\r
575	--+-----------------------------------------+\r
576	--\| unused outputs \|\r
577	--+-----------------------------------------+\r
578	-- #stop: Curret TARGET indicates to Master stop current transaction\r
579	-- #perr:\r
580	-- #serr:\r
581	\r
582	perr <= 'Z';\r
583	serr <= 'Z';\r
584	stop <= 'Z';\r
585	intb <= '0' when ( wb_int_i = '1' ) else 'Z';\r
586	\r
587	\r
588	end rtl;\r
589	\r
590	\r