[raggedstone] / ethernet / source / pci / timescale.v

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////  File name "timescale.v"                                     ////
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//
// CVS Revision History
//
// $Log: timescale.v,v $
// Revision 1.1  2007-03-20 17:50:56  sithglan
// add shit
//
// Revision 1.2  2002/02/01 15:25:13  mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.1  2001/10/05 08:11:22  mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
//

// timescale directive is included in all core's modules for simulation purposes
`timescale 1ns/1ps
Commit	Line	Data
40a1f26c	1	//////////////////////////////////////////////////////////////////////
	2	//// ////
	3	//// File name "timescale.v" ////
	4	//// ////
	5	//////////////////////////////////////////////////////////////////////
	6	//
	7	// CVS Revision History
	8	//
	9	// $Log: timescale.v,v $
	10	// Revision 1.1 2007-03-20 17:50:56 sithglan
	11	// add shit
	12	//
	13	// Revision 1.2 2002/02/01 15:25:13 mihad
	14	// Repaired a few bugs, updated specification, added test bench files and design document
	15	//
	16	// Revision 1.1 2001/10/05 08:11:22 mihad
	17	// Updated all files with inclusion of timescale file for simulation purposes.
	18	//
	19	//
	20
	21	// timescale directive is included in all core's modules for simulation purposes
	22	`timescale 1ns/1ps