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377c0242 1-- J.STELZNER\r
2-- INFORMATIK-3 LABOR\r
3-- 23.08.2006\r
4-- File: COMM_DEC.VHD\r
5\r
6library ieee;\r
7use ieee.std_logic_1164.all ;\r
8\r
9entity COMM_DEC is\r
10 port\r
11 (\r
12 PCI_CLOCK :in std_logic; \r
13 PCI_RSTn :in std_logic; \r
14 MY_ADDR :in std_logic;\r
15 IDSEL_REG :in std_logic;\r
16 FRAME_REGn :in std_logic;\r
17 IO_SPACE :in std_logic;\r
18 AD_REG :in std_logic_vector(31 downto 0);\r
19 CBE_REGn :in std_logic_vector( 3 downto 0);\r
20 LAR :out std_logic;--LOAD_ADDR_REG\r
21 IO_READ :out std_logic;\r
22 IO_WRITE :out std_logic;\r
23 CONF_READ :out std_logic;\r
24 CONF_WRITE :out std_logic;\r
25 SERR_CHECK :out std_logic\r
26 );\r
27end entity COMM_DEC ;\r
28\r
29architecture COMM_DEC_DESIGN of COMM_DEC is\r
30\r
31\r
32--PCI Bus Commands \r
33--C/BE[3..0] Command Type\r
34--------------------------------------\r
35-- 0000 Interrupt Acknowledge\r
36-- 0001 Special Cycle\r
37-- 0010 I/O Read\r
38-- 0011 I/O Write\r
39-- 0100 Reserved\r
40-- 0101 Reserved\r
41-- 0110 Memory Read\r
42-- 0111 Memory Write\r
43--\r
44-- 1000 Reserved\r
45-- 1001 Reserved\r
46-- 1010 Configuration Read\r
47-- 1011 Configuration Write\r
48-- 1100 Memory Read Multiple \r
49-- 1101 Dual Address Cycle\r
50-- 1110 Memory Read Line\r
51-- 1111 Memory Write and Invalidate\r
52\r
53\r
54--PCI Byte Enable \r
55--C/BE[3..0] gueltige Datenbits \r
56-------------------------------\r
57-- 0000 AD 31..0\r
58-- 1000 AD 23..0\r
59-- 1100 AD 15..0\r
60-- 1110 AD 7..0\r
61\r
62 constant cmd_int_ack :std_logic_vector(3 downto 0) := "0000";\r
63 constant cmd_sp_cyc :std_logic_vector(3 downto 0) := "0001";\r
64 constant cmd_io_read :std_logic_vector(3 downto 0) := "0010";\r
65 constant cmd_io_write :std_logic_vector(3 downto 0) := "0011";\r
66 constant cmd_res_4 :std_logic_vector(3 downto 0) := "0100";\r
67 constant cmd_res_5 :std_logic_vector(3 downto 0) := "0101";\r
68 constant cmd_mem_read :std_logic_vector(3 downto 0) := "0110";\r
69 constant cmd_mem_write :std_logic_vector(3 downto 0) := "0111";\r
70 constant cmd_res_8 :std_logic_vector(3 downto 0) := "1000";\r
71 constant cmd_res_9 :std_logic_vector(3 downto 0) := "1001";\r
72 constant cmd_conf_read :std_logic_vector(3 downto 0) := "1010";\r
73 constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011";\r
74 constant cmd_mem_read_m :std_logic_vector(3 downto 0) := "1100";\r
75 constant cmd_du_adr_cyc :std_logic_vector(3 downto 0) := "1101";\r
76 constant cmd_mem_read_l :std_logic_vector(3 downto 0) := "1110";\r
77 constant cmd_mem_write_i :std_logic_vector(3 downto 0) := "1111";\r
78\r
79 signal START :std_logic; \r
80 signal FRAME_REG_REGn :std_logic; \r
81\r
82 signal SIG_IO_READ :std_logic; \r
83 signal SIG_IO_WRITE :std_logic; \r
84 signal SIG_CONF_READ :std_logic; \r
85 signal SIG_CONF_WRITE :std_logic; \r
86\r
87begin\r
88\r
89 process (PCI_CLOCK, PCI_RSTn) \r
90 begin\r
91 if PCI_RSTn = '0' then FRAME_REG_REGn <= '1'; \r
92 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
93\r
94 FRAME_REG_REGn <= FRAME_REGn; \r
95\r
96 end if;\r
97 end process;\r
98\r
99\r
100 START <= (not FRAME_REGn) and FRAME_REG_REGn; \r
101\r
102\r
103\r
104 SIG_IO_READ <= '1' when START = '1'\r
105 and IO_SPACE = '1'\r
106 and CBE_REGn = cmd_io_read \r
107 and MY_ADDR = '1'\r
108 else '0'; \r
109\r
110\r
111 SIG_IO_WRITE <= '1' when START = '1'\r
112 and IO_SPACE = '1'\r
113 and CBE_REGn = cmd_io_write\r
114 and MY_ADDR = '1'\r
115 else '0'; \r
116\r
117\r
118 SIG_CONF_READ <= '1' when START = '1'\r
119 and AD_REG(1 downto 0) = "00"\r
120 and CBE_REGn = cmd_conf_read\r
121 and IDSEL_REG = '1'\r
122 \r
123 else '0'; \r
124\r
125\r
126 SIG_CONF_WRITE <= '1' when START = '1'\r
127 and AD_REG(1 downto 0) = "00"\r
128 and CBE_REGn = cmd_conf_write\r
129 and IDSEL_REG = '1'\r
130 else '0'; \r
131\r
132 LAR <= START;\r
133\r
134 SERR_CHECK <= SIG_IO_READ or SIG_IO_WRITE or SIG_CONF_READ or SIG_CONF_WRITE; \r
135\r
136 IO_READ <= SIG_IO_READ;\r
137 IO_WRITE <= SIG_IO_WRITE; \r
138 CONF_READ <= SIG_CONF_READ; \r
139 CONF_WRITE <= SIG_CONF_WRITE;\r
140\r
141end architecture COMM_DEC_DESIGN ;\r
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