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377c0242 1-- VHDL model created from schematic pci_top.sch -- Jan 09 09:34:14 2007\r
2\r
3\r
4\r
5LIBRARY ieee;\r
6\r
7USE ieee.std_logic_1164.ALL;\r
8USE ieee.numeric_std.ALL;\r
9\r
10\r
11entity PCI_TOP is\r
12 Port ( FLAG : In std_logic_vector (7 downto 0);\r
13 INT_REG : In std_logic_vector (7 downto 0);\r
14 PCI_CBEn : In std_logic_vector (3 downto 0);\r
15 PCI_CLOCK : In std_logic;\r
16 PCI_FRAMEn : In std_logic;\r
17 PCI_IDSEL : In std_logic;\r
18 PCI_IRDYn : In std_logic;\r
19 PCI_RSTn : In std_logic;\r
20 R_FIFO_Q : In std_logic_vector (7 downto 0);\r
21 REVISON_ID : In std_logic_vector (7 downto 0);\r
22 VENDOR_ID : In std_logic_vector (15 downto 0);\r
23 PCI_AD : InOut std_logic_vector (31 downto 0);\r
24 PCI_PAR : InOut std_logic;\r
25 AD_REG : Out std_logic_vector (31 downto 0);\r
26 DEVSELn : Out std_logic;\r
27 FIFO_RDn : Out std_logic;\r
28 PCI_DEVSELn : Out std_logic;\r
29 PCI_PERRn : Out std_logic;\r
30 PCI_SERRn : Out std_logic;\r
31 PCI_STOPn : Out std_logic;\r
32 PCI_TRDYn : Out std_logic;\r
33 READ_SEL : Out std_logic_vector (1 downto 0);\r
34 READ_XX1_0 : Out std_logic;\r
35 READ_XX3_2 : Out std_logic;\r
36 READ_XX5_4 : Out std_logic;\r
37 READ_XX7_6 : Out std_logic;\r
38 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
39 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
40 REG_OUT_XX7 : Out std_logic_vector (7 downto 0);\r
41 TRDYn : Out std_logic;\r
42 WRITE_XX1_0 : Out std_logic;\r
43 WRITE_XX3_2 : Out std_logic;\r
44 WRITE_XX5_4 : Out std_logic;\r
45 WRITE_XX7_6 : Out std_logic );\r
46end PCI_TOP;\r
47\r
48architecture SCHEMATIC of PCI_TOP is\r
49\r
50 SIGNAL gnd : std_logic := '0';\r
51 SIGNAL vcc : std_logic := '1';\r
52\r
53 signal IRDY_REGn : std_logic;\r
54 signal IO_WR_COM : std_logic;\r
55 signal TRDYn_DUMMY : std_logic;\r
56 signal READ_XX3_2_DUMMY : std_logic;\r
57 signal USER_DATA_OUT : std_logic_vector (31 downto 0);\r
58 signal CBE_REGn : std_logic_vector (3 downto 0);\r
59 signal AD_REG_DUMMY : std_logic_vector (31 downto 0);\r
60 signal ADDR_REG : std_logic_vector (31 downto 0);\r
61 signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);\r
62\r
63 component USER_IO\r
64 Port ( AD_REG : In std_logic_vector (31 downto 0);\r
65 ADDR_REG : In std_logic_vector (31 downto 0);\r
66 CBE_REGn : In std_logic_vector (3 downto 0);\r
67 FLAG : In std_logic_vector (7 downto 0);\r
68 INT_REG : In std_logic_vector (7 downto 0);\r
69 IO_WR_COM : In std_logic;\r
70 IRDY_REGn : In std_logic;\r
71 PCI_CLK : In std_logic;\r
72 R_FIFO_Q : In std_logic_vector (7 downto 0);\r
73 READ_SEL : In std_logic_vector (1 downto 0);\r
74 TRDYn : In std_logic;\r
75 READ_XX1_0 : Out std_logic;\r
76 READ_XX3_2 : Out std_logic;\r
77 READ_XX5_4 : Out std_logic;\r
78 READ_XX7_6 : Out std_logic;\r
79 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
80 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
81 REG_OUT_XX7 : Out std_logic_vector (7 downto 0);\r
82 USER_DATA_OUT : Out std_logic_vector (31 downto 0);\r
83 WRITE_XX1_0 : Out std_logic;\r
84 WRITE_XX3_2 : Out std_logic;\r
85 WRITE_XX5_4 : Out std_logic;\r
86 WRITE_XX7_6 : Out std_logic );\r
87 end component;\r
88\r
89 component PCI_INTERFACE\r
90 Port ( PCI_CBEn : In std_logic_vector (3 downto 0);\r
91 PCI_CLOCK : In std_logic;\r
92 PCI_FRAMEn : In std_logic;\r
93 PCI_IDSEL : In std_logic;\r
94 PCI_IRDYn : In std_logic;\r
95 PCI_RSTn : In std_logic;\r
96 READ_FIFO : In std_logic;\r
97 REVISON_ID : In std_logic_vector (7 downto 0);\r
98 USER_DATA_OUT : In std_logic_vector (31 downto 0);\r
99 VENDOR_ID : In std_logic_vector (15 downto 0);\r
100 PCI_AD : InOut std_logic_vector (31 downto 0);\r
101 PCI_PAR : InOut std_logic;\r
102 AD_REG : Out std_logic_vector (31 downto 0);\r
103 ADDR_REG : Out std_logic_vector (31 downto 0);\r
104 CBE_REGn : Out std_logic_vector (3 downto 0);\r
105 DEVSELn : Out std_logic;\r
106 FIFO_RDn : Out std_logic;\r
107 IO_WR_COM : Out std_logic;\r
108 IRDY_REGn : Out std_logic;\r
109 PCI_DEVSELn : Out std_logic;\r
110 PCI_PERRn : Out std_logic;\r
111 PCI_SERRn : Out std_logic;\r
112 PCI_STOPn : Out std_logic;\r
113 PCI_TRDYn : Out std_logic;\r
114 READ_SEL : Out std_logic_vector (1 downto 0);\r
115 TRDYn : Out std_logic );\r
116 end component;\r
117\r
118begin\r
119\r
120 READ_SEL <= READ_SEL_DUMMY;\r
121 AD_REG <= AD_REG_DUMMY;\r
122 READ_XX3_2 <= READ_XX3_2_DUMMY;\r
123 TRDYn <= TRDYn_DUMMY;\r
124\r
125 I19 : USER_IO\r
126 Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
127 ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
128 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
129 FLAG(7 downto 0)=>FLAG(7 downto 0),\r
130 INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
131 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,\r
132 PCI_CLK=>PCI_CLOCK,\r
133 R_FIFO_Q(7 downto 0)=>R_FIFO_Q(7 downto 0),\r
134 READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),\r
135 TRDYn=>TRDYn_DUMMY, READ_XX1_0=>READ_XX1_0,\r
136 READ_XX3_2=>READ_XX3_2_DUMMY, READ_XX5_4=>READ_XX5_4,\r
137 READ_XX7_6=>READ_XX7_6,\r
138 REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0(7 downto 0),\r
139 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
140 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
141 USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
142 WRITE_XX1_0=>WRITE_XX1_0, WRITE_XX3_2=>WRITE_XX3_2,\r
143 WRITE_XX5_4=>WRITE_XX5_4, WRITE_XX7_6=>WRITE_XX7_6 );\r
144 I10 : PCI_INTERFACE\r
145 Port Map ( PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
146 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
147 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
148 PCI_RSTn=>PCI_RSTn, READ_FIFO=>READ_XX3_2_DUMMY,\r
149 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
150 USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
151 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
152 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
153 PCI_PAR=>PCI_PAR,\r
154 AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
155 ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
156 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
157 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
158 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,\r
159 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,\r
160 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,\r
161 PCI_TRDYn=>PCI_TRDYn,\r
162 READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),\r
163 TRDYn=>TRDYn_DUMMY );\r
164\r
165end SCHEMATIC;\r
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